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1. 发明授权

US4981813A Pad oxide protect sealed interface isolation process 失效
标题翻译：垫氧化物保护密封接口隔离工艺
公开(公告)号：US4981813A
公开(公告)日：1991-01-01
申请号：US279343
申请日：1988-12-02
申请人： Frank R. Bryant , Yu-Pin Han , Fu-Tai Liou , Tsiu C. Chan
发明人： Frank R. Bryant , Yu-Pin Han , Fu-Tai Liou , Tsiu C. Chan
IPC分类号： H01L21/32 , H01L21/762
CPC分类号： H01L21/76205 , H01L21/32
摘要： Field oxide regions are formed between active regions of a silicon substrate by forming over the substrate a sandwich of silicon dioxide, silicon nitride and silicon dioxide layers, opening the layers to expose a portion of the silicon substrate, removing a layer of the exposed substrate, forming side wall spacers on the edges of the opening, removing a layer of the silicon substrate exposed between the side wall spacers, and then reaching the exposed substrate for the thermal oxidation of the exposed substrate for forming the field oxide region. In those structures in which the field oxide is buried in the substrate as shown in FIG. 12, it may be feasible to use thicker field oxide regions and thereby to reduce the need for the heavily doped surface layer under the field oxide.
摘要翻译：通过在衬底上形成二氧化硅，氮化硅和二氧化硅层的夹层来形成在硅衬底的有源区之间的场氧化物区域，打开这些层以露出硅衬底的一部分，去除暴露的衬底的一层，在开口的边缘上形成侧壁间隔物，去除暴露在侧壁间隔物之间的硅衬底层，然后到达暴露的衬底，用于暴露衬底的热氧化以形成场氧化物区域。在如图1所示的那些场地氧化物埋在衬底中的那些结构中。如图12所示，可以使用较厚的场氧化物区域，从而减少对场氧化物下的重掺杂表面层的需要。

2. 发明授权

US5256895A Pad oxide protect sealed interface isolation 失效
标题翻译：垫氧化物保护密封接口隔离
公开(公告)号：US5256895A
公开(公告)日：1993-10-26
申请号：US863519
申请日：1992-03-31
申请人： Frank R. Bryant , Yu-Pin Han , Fu-Tai Liou
发明人： Frank R. Bryant , Yu-Pin Han , Fu-Tai Liou
IPC分类号： H01L21/32 , H01L21/762 , H01L27/12 , H01L23/48 , H01L29/40
CPC分类号： H01L21/32 , H01L21/76205
摘要： Field oxide regions are formed between drive regions of a silicon substrate by forming over the substrate a sandwich of silicon dioxide, silicon nitride and silicon dioxide layers, opening the layers to expose a portion of the silicon substrate, removing a layer of the exposed substrate, forming side wall spacers on the edges of the opening, removing a layer of the silicon substrate exposed between the side wall spacers, and then reaching the exposed substrate for the thermal oxidation of the exposed substrate for forming the field oxide region. In those structures in which the field oxide is buried in the substrate as shown in FIG. 12, it may be feasible to use thicker field oxide regions and thereby to reduce the need for the heavily doped surface layer under the field oxide.
摘要翻译：通过在衬底上形成二氧化硅，氮化硅和二氧化硅层的夹层来形成在硅衬底的驱动区之间的场氧化物区域，打开这些层以暴露硅衬底的一部分，去除暴露的衬底的一层，在开口的边缘上形成侧壁间隔物，去除暴露在侧壁间隔物之间的硅衬底层，然后到达暴露的衬底，用于暴露衬底的热氧化以形成场氧化物区域。在如图1所示的那些场地氧化物埋在衬底中的那些结构中。如图12所示，可以使用较厚的场氧化物区域，从而减少对场氧化物下的重掺杂表面层的需要。

3. 发明授权

US4771014A Process for manufacturing LDD CMOS devices 失效
标题翻译：制造LDD CMOS器件的工艺
公开(公告)号：US4771014A
公开(公告)日：1988-09-13
申请号：US99144
申请日：1987-09-18
申请人： Fu-Tai Liou , Yu-Pin Han , Frank R. Bryant
发明人： Fu-Tai Liou , Yu-Pin Han , Frank R. Bryant
IPC分类号： H01L27/092 , H01L21/8238 , H01L21/265 , H01L27/00
CPC分类号： H01L21/823878 , H01L27/0928
摘要： A method for making a CMOS integrated circuit device saves on masking steps by using unmasked blanket implantations at various steps of the process, such as setting the threshold voltages of the transistors, forming a lightly doped drain for the N-channel transistor, and for forming the source/drain regions of the N-type transistor.

4. 发明授权

US5057463A Thin oxide structure and method 失效
标题翻译：薄氧化物结构和方法
公开(公告)号：US5057463A
公开(公告)日：1991-10-15
申请号：US486121
申请日：1990-02-28
申请人： Frank R. Bryant , Fu-Tai Liou
发明人： Frank R. Bryant , Fu-Tai Liou
IPC分类号： H01L21/316
CPC分类号： H01L21/02238 , H01L21/02255 , H01L21/31662 , Y10S148/118
摘要： A method for forming a thin oxide layer structure includes the step of first growing a dry oxide layer. A layer grown in steam and chlorine is formed next, followed by a final dry oxide layer. An anneal step in an inert gas further improves the quality of the oxide layer. The structure formed by such a process provides a layer of steam grown oxide sandwiched between two layers of oxide grown in a dry atmosphere.
摘要翻译：形成薄氧化物层结构的方法包括首先生长干氧化物层的步骤。接下来形成在蒸汽和氯气中生长的层，随后是最后的干燥氧化物层。惰性气体中的退火步骤进一步提高了氧化物层的质量。通过这种方法形成的结构提供了在干燥气氛中生长的两层氧化物之间的蒸汽生长氧化层。

5. 发明授权

US4863562A Method for forming a non-planar structure on the surface of a semiconductor substrate 失效
标题翻译：在半导体衬底的表面上形成非平面结构的方法
公开(公告)号：US4863562A
公开(公告)日：1989-09-05
申请号：US155148
申请日：1988-02-11
申请人： Frank R. Bryant , Fu-Tai Liou
发明人： Frank R. Bryant , Fu-Tai Liou
IPC分类号： H01L21/32 , H01L21/336 , H01L21/762
CPC分类号： H01L21/32 , H01L21/76202 , H01L29/66795
摘要： A method for increasing the width of a transistor includes first forming a nitride cap (14) over the substrate (10) and then forming trenches (24) and (26) on either side of the cap (14) and having tapered sidewalls (28) and (30). A conformal layer of nitride (32) is formed over the substrate and then anisotropically etched to form sidewall layers (34) and (36). Field oxide is grown in the trenches with birds beaks (42) and (44) extending upward under the sidewall layers (34) and (36). A portion of the sidewalls (28) and (30) of the trenches remain such that the overall surface area between the edges of the birds beaks (42) and (44) is increased. A layer of strip oxide is then grown on the substrate to provide rounded edges (47) and (49). The strip oxide is then removed by a fifty percent over etch to cause the birds beaks (42) and (44) to recede, thus further increasing the surface area. The gate electrode of a transistor (54) can then be disposed thereacross, thus increasing the width of the transistor for a given silicon surface area in the initial material.

6. 发明授权

US5894160A Method of forming a landing pad structure in an integrated circuit 失效
公开(公告)号：US5894160A
公开(公告)日：1999-04-13
申请号：US725621
申请日：1996-10-03
申请人： Tsiu C. Chan , Frank R. Bryant , Loi N. Nguyen
发明人： Tsiu C. Chan , Frank R. Bryant , Loi N. Nguyen
IPC分类号： H01L21/28 , H01L21/285 , H01L21/3205 , H01L21/768 , H01L21/8239 , H01L23/485 , H01L23/52 , H01L23/522 , H01L23/528 , H01L27/02 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113
CPC分类号： H01L21/28 , H01L21/28525 , H01L21/76895 , H01L23/485 , H01L23/5226 , H01L23/5283 , H01L27/0248 , H01L27/1052 , H01L2924/0002
摘要： A method is provided for forming an improved landing pad of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A first opening is formed through a first dielectric layer to expose a portion of a diffused region. A first polysilicon landing pad is formed over the first dielectric layer and in the opening. This landing pad will provide for smaller geometries and meet stringent design rules such as that for contact space to gate. A dielectric pocket is formed over the polysilicon landing pad over the active region. A second conductive landing pad is formed over the polysilicon landing pad and the dielectric pocket. A second dielectric layer is formed over the landing pad having a second opening therethrough exposing a portion of the landing pad. A conductive contact, such as aluminum, is formed in the second contact opening. The conductive contact will electrically connect with the diffused region through the landing pad. Misalignment of the conductive contact opening over the landing pad may be tolerated without invading design rules. The landing pad and the dielectric pocket will enhance planarization to provide for better step coverage of the metal contact in the second opening.

7. 发明授权

US5489797A Local interconnect structure 失效
标题翻译：本地互连结构
公开(公告)号：US5489797A
公开(公告)日：1996-02-06
申请号：US420353
申请日：1995-04-11
申请人： Tsiu C. Chan , Frank R. Bryant , John L. Walters
发明人： Tsiu C. Chan , Frank R. Bryant , John L. Walters
IPC分类号： H01L21/768 , H01L23/532 , H01L27/11 , H01L29/76 , H01L29/94
CPC分类号： H01L27/1104 , H01L21/76895 , H01L23/53271 , H01L2924/0002 , Y10S257/903
摘要： An interconnect structure, and method for forming same, is suitable for use in integrated circuits such as SRAM devices. The structure uses masking of a polycrystalline silicon interconnect level to move a P-N junction to a region within a polycrystalline silicon interconnect line, rather than at the substrate. This P-N junction can then be shorted out using a refractory metal silicide formed on the polycrystalline silicon interconnect structure.
摘要翻译：互连结构及其形成方法适用于诸如SRAM器件的集成电路。该结构使用多晶硅互连电平的掩模将P-N结移动到多晶硅互连线内的区域，而不是在衬底处。然后可以使用形成在多晶硅互连结构上的难熔金属硅化物来短路该P-N结。

8. 发明授权

US5196909A Capacitor for DRAM cell 失效
标题翻译： DRAM单元电容器
公开(公告)号：US5196909A
公开(公告)日：1993-03-23
申请号：US697227
申请日：1991-05-07
申请人： Tsiu C. Chan , Frank R. Bryant
发明人： Tsiu C. Chan , Frank R. Bryant
IPC分类号： H01L21/02 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10844 , H01L27/10817 , H01L28/40
摘要： A capacitor suitable for use with a DRAM memory cell is composed of multiple layers of polycrystalline silicon. The storage node is formed from a polycrystalline silicon layer sandwiched between two polysilicon ground plate layers. Such a structure nearly doubles the capacitance for a given chip surface area used. First the bottom polycrystalline silicon plate layer is fabricated, followed by an isolation step and fabrication of the storage node polycrystalline silicon layer. Following another isolation step, the polycrystalline silicon top plate layer is then formed and connected to the bottom plate layer.
摘要翻译：适用于DRAM存储单元的电容器由多层多晶硅组成。存储节点由夹在两个多晶硅接地板层之间的多晶硅层形成。这种结构对于所使用的给定芯片表面积几乎使电容增加一倍。首先制造底部多晶硅板层，然后进行隔离步骤和存储节点多晶硅层的制造。在另一隔离步骤之后，然后形成多晶硅顶板层并将其连接到底板层。

9. 发明授权

US5702979A Method of forming a landing pad structure in an integrated circuit 失效
标题翻译：在集成电路中形成着陆焊盘结构的方法
公开(公告)号：US5702979A
公开(公告)日：1997-12-30
申请号：US361760
申请日：1994-12-22
申请人： Tsiu C. Chan , Frank R. Bryant , Loi N. Nguyen
发明人： Tsiu C. Chan , Frank R. Bryant , Loi N. Nguyen
IPC分类号： H01L21/28 , H01L21/285 , H01L21/3205 , H01L21/768 , H01L21/8239 , H01L23/485 , H01L23/52 , H01L23/522 , H01L23/528 , H01L27/02 , H01L21/44
CPC分类号： H01L21/28 , H01L21/28525 , H01L21/76895 , H01L23/485 , H01L23/5226 , H01L23/5283 , H01L27/0248 , H01L27/1052 , H01L2924/0002
摘要： A method is provided for forming an improved landing pad of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A first opening is formed through a first dielectric layer to expose a portion of a diffused region. A first polysilicon landing pad is formed over the first dielectric layer and in the opening. This landing pad will provide for smaller geometries and meet stringent design rules such as that for contact space to gate. A dielectric pocket is formed over the polysilicon landing pad over the active region. A second conductive landing pad is formed over the polysilicon landing pad and the dielectric pocket. A second dielectric layer is formed over the landing pad having a second opening therethrough exposing a portion of the landing pad. A conductive contact, such as aluminum, is formed in the second contact opening. The conductive contact will electrically connect with the diffused region through the landing pad. Misalignment of the conductrive contact opening over the landing pad may be tolerated without invading design rules. The landing pad and the dielectric pocket will enhance planarization to provide for better step coverage of the metal contact in the second opening.
摘要翻译：提供一种用于形成半导体集成电路的改进的着陆焊盘的方法，以及根据该集成电路形成的集成电路。通过第一介电层形成第一开口以暴露扩散区域的一部分。在第一介电层上和开口中形成第一多晶硅着陆焊盘。该着陆垫将提供更小的几何形状，并满足严格的设计规则，例如接触空间到门。在有源区上方的多晶硅着陆垫上形成电介质袋。在多晶硅着陆焊盘和电介质槽上方形成第二导电焊盘。第二电介质层形成在着陆焊盘上，具有通过其暴露出一部分着陆焊盘的第二开口。在第二接触开口中形成诸如铝的导电接触。导电触点将通过着陆焊盘与扩散区域电连接。可以容忍在着陆垫上的导电触头开口的不对准，而不会侵入设计规则。着陆垫和电介质袋将增强平面化，以提供第二开口中的金属接触件的更好的台阶覆盖。

10. 发明授权

US5448091A Method of making contact alignment for nonvolatile memory devices 失效
标题翻译：非易失性存储器件接触对准方法
公开(公告)号：US5448091A
公开(公告)日：1995-09-05
申请号：US307475
申请日：1994-09-16
申请人： Frank R. Bryant , Tsiu C. Chan
发明人： Frank R. Bryant , Tsiu C. Chan
IPC分类号： G11C17/00 , H01L21/768 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , H01L29/68
CPC分类号： H01L21/76802 , H01L27/115 , Y10S257/90
摘要： A layout and fabrication technique for EPROMs and similar devices includes a preferred technique for partially self-aligning bit line contacts. In addition, a self-aligned, buried Vss line is provided which is in contact with the substrate for its entire length. This provides a highly conductive Vss line, allowing the size of such line to be diminished. The use of a buried Vss contact line and a partially self-aligned bit line contact contributes to a device layout having minimum cell sizes for a given feature size.
摘要翻译： EPROM和类似器件的布局和制造技术包括用于部分自对准位线触点的优选技术。另外，提供了自对准埋置的Vss线，其与衬底的整个长度接触。这提供了高导电性Vss线，允许这种线的尺寸减小。使用埋入的Vss接触线和部分自对准位线接触有助于针对给定特征尺寸具有最小单元尺寸的器件布局。

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