专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07130946B2 Configuration and method having a first device and a second device connected to the first device through a cross bar 有权
标题翻译：配置和方法具有通过横杆连接到第一设备的第一设备和第二设备
公开(公告)号：US07130946B2
公开(公告)日：2006-10-31
申请号：US10600554
申请日：2003-06-20
申请人： Gupta Abhay , Frank Hellwig , Dietmar König , Richard Tuck
发明人： Gupta Abhay , Frank Hellwig , Dietmar König , Richard Tuck
IPC分类号： G06F13/00
CPC分类号： G06F13/4022
摘要： A configuration and method for operating the configuration includes first and second devices connected to one another through a cross bar and accessing one another through the cross bar for reading and/or writing data. When a read access to the second device occurs, the first device reads the data emitted from the second device when it receives a ready signal produced by the second device and supplied to the first device through the cross bar, and, when a write access occurs from the first device to the second device, the first device emits the data to be written to the second device when it receives a ready signal produced by the second device and supplied to the first device through the cross bar and the second device reads the data emitted from the first device when it receives a data valid signal produced by the first device and supplied to the second device through the cross bar.
摘要翻译：用于操作配置的配置和方法包括通过横杆彼此连接并通过横杆彼此接合以便读取和/或写入数据的第一和第二设备。当发生对第二设备的读访问时，第一设备在接收到由第二设备产生的就绪信号并通过交叉条提供给第一设备时读取从第二设备发射的数据，并且当发生写访问时从第一设备到第二设备，当第一设备接收到由第二设备产生的就绪信号并通过交叉条提供给第一设备时，第一设备发送要写入第二设备的数据，并且第二设备读取数据当从第一装置接收到由第一装置产生的数据有效信号并通过交叉条提供给第二装置时从第一装置发射。

2. 发明申请

US20050120348A1 Method of determining information about the processes which run in a program-controlled unit during the execution of a program by the program-controlled unit 审中-公开
标题翻译：在由程序控制单元执行程序期间确定在程序控制单元中运行的处理的信息的方法
公开(公告)号：US20050120348A1
公开(公告)日：2005-06-02
申请号：US10989880
申请日：2004-11-16
申请人： Albrecht Mayer , Harry Siebert , Frank Hellwig
发明人： Albrecht Mayer , Harry Siebert , Frank Hellwig
IPC分类号： G06F11/34 , G06F9/46
CPC分类号： G06F11/3466
摘要： Method of determining information about the processes which run in a program-controlled unit during the execution of a program by the program-controlled unit A description is given of a method of determining information about the processes which run in a program-controlled unit during the execution of a program by the program-controlled unit. The method described is distinguished by the fact that identical items of individual information about processes of the same type are combined to form a single item of overall information. As a result, the desired information about the processes of interest can be procured with considerably less expenditure than was the case hitherto.
摘要翻译：在由程序控制单元执行程序期间确定在程序控制单元中运行的处理的信息的方法给出了一种确定关于在程序控制单元期间在程序控制单元中运行的处理的信息的方法由程序控制单元执行程序。所描述的方法的区别在于，将相同类型的进程的单个信息的相同项目组合以形成单个总体信息项。因此，与目前的情况相比，可以以相当少的支出获得关于感兴趣的过程的所需信息。

3. 发明授权

US08352804B2 Systems and methods for secure interrupt handling 有权
标题翻译：用于安全中断处理的系统和方法
公开(公告)号：US08352804B2
公开(公告)日：2013-01-08
申请号：US12784015
申请日：2010-05-20
申请人： Frank Hellwig , Antonio Vilela
发明人： Frank Hellwig , Antonio Vilela
IPC分类号： G06F11/30 , G06F11/00
CPC分类号： G06F13/26
摘要： The invention relates to systems for secure interrupt handling, a method for verifying a priority of a winning service request node and a method and an apparatus for verifying integrity of service requests.In accordance with an aspect of the invention, there is provided a method for verifying a priority of a winning service request node (SRN) established in an arbitration between a plurality of service request nodes (SRNs) performed by an interrupt controller, the method comprising: storing the priority of the winning SRN in the interrupt controller; encoding the priority of the winning SRN, wherein the encoding allows for error detection; transmitting the encoded priority from the winning SRN to the interrupt controller; and verifying the priority of the winning SRN by comparing the encoded priority transmitted by the winning SRN with the priority of the winning SRN established in the arbitration and stored in the interrupt controller.
摘要翻译：本发明涉及用于安全中断处理的系统，用于验证获胜服务请求节点的优先级的方法以及用于验证服务请求的完整性的方法和装置。根据本发明的一个方面，提供了一种用于验证在由中断控制器执行的多个服务请求节点（SRN）之间的仲裁中建立的获胜服务请求节点（SRN）的优先级的方法，所述方法包括：：将获胜的SRN的优先级存储在中断控制器中; 编码获胜SRN的优先级，其中编码允许错误检测; 将所述编码优先级从所述获胜SRN发送到所述中断控制器; 以及通过将获胜的SRN发送的编码优先级与在仲裁中建立并存储在中断控制器中的获胜SRN的优先级进行比较来验证获胜SRN的优先级。

4. 发明授权

US07373445B2 Method and apparatus for allocating bus access rights in multimaster bus systems 有权
标题翻译：在多主机总线系统中分配总线访问权限的方法和装置
公开(公告)号：US07373445B2
公开(公告)日：2008-05-13
申请号：US11087062
申请日：2005-03-21
申请人： Frank Hellwig , Dietmar König
发明人： Frank Hellwig , Dietmar König
IPC分类号： G06F13/00
CPC分类号： G06F13/362
摘要： A method for allocating bus access rights is used in a multimaster bus system wherein addresses are explicitly allocated to master devices and each master device is assigned a priority value from an organized priority list of priority values. Requests from at least one master device to use the bus system to access a slave device are received, and the priority values of all requesting master devices are compared. If a sole requesting master device has the highest priority value access to the respective slave device is granted to that master device. If a plurality of requesting master devices have the same highest priority value access is successively granted to the requesting master devices having the same highest priority value on the basis of the address allocation of the master devices.
摘要翻译：在多主机总线系统中使用分配总线访问权限的方法，其中地址被明确地分配给主设备，并且每个主设备从优先级的有组织的优先级列表中分配优先级值。接收来自至少一个主设备的使用总线系统访问从设备的请求，并且比较所有请求主设备的优先级值。如果唯一请求的主设备具有最高优先级值，则向该主设备授予对相应从设备的访问权限。如果多个请求主设备具有相同的最高优先级值，则基于主设备的地址分配，连续授予具有相同最高优先级值的请求主设备的访问。

5. 发明授权

US07023760B2 Memory arrangement for processing data, and method 有权
标题翻译：用于处理数据的内存安排和方法
公开(公告)号：US07023760B2
公开(公告)日：2006-04-04
申请号：US10878172
申请日：2004-06-28
申请人： Frank Hellwig
发明人： Frank Hellwig
IPC分类号： G11C8/00
CPC分类号： G11C7/222 , G11C7/22 , G11C11/4076
摘要： The invention relates to a memory arrangement for processing data and to a method for operating this memory arrangement. The inventive method involves a control signal being transferred together with the data on, with a change in the control signal activating the DLL circuit and synchronizing it to a clock. In this case, the DLL circuit stipulates a sampling time for the data. In line with the invention, after a predetermined length of time within which no data have been read from the memory, the memory is accessed artificially in order to generate a change in the control signal for the DLL circuit.
摘要翻译：本发明涉及一种用于处理数据的存储装置和一种用于操作该存储装置的方法。本发明的方法涉及控制信号与数据一起转移，控制信号的变化激活DLL电路并将其同步到时钟。在这种情况下，DLL电路规定了数据的采样时间。根据本发明，在没有从存储器读取数据的预定时间长度之后，人为地访问存储器以便产生用于DLL电路的控制信号的改变。

6. 发明申请

US20050223147A1 Method and apparatus for allocating bus access rights in multimaster bus systems 有权
标题翻译：在多主机总线系统中分配总线访问权限的方法和装置
公开(公告)号：US20050223147A1
公开(公告)日：2005-10-06
申请号：US11087062
申请日：2005-03-21
申请人： Frank Hellwig , Dietmar Konig
发明人： Frank Hellwig , Dietmar Konig
IPC分类号： G06F13/00 , G06F13/362 , G06F13/374
CPC分类号： G06F13/362
摘要： A method for allocating bus access rights in a multimaster bus system (2), having the following steps: addresses (MASTER0-MASTER 15) are explicitly allocated to master devices (3-1, . . . 3-N) in the multimaster bus system, a priority value (P0, . . . P15) from an organized priority list (5) of priority values (P0 . . . P15) is assigned to each master device (3-1, . . . 3-N) provided in the multimaster bus system (2), requests from at least one master device (3-1, . . . 3-N) to use the bus system (2) to access a slave device (4-1, . . . 4-M) are received, the priority values (P0, . . . P15) of all requesting master devices (3-1, . . . 3-N) are compared, if a sole requesting master device (3-1, . . . 3-N) has the highest priority value (P0, . . . P15): sole access to the respective slave device (4-1, . . . 4-M) is granted to the requesting master device (3-1, . . . 3-N) which has the highest priority value (P0, . . . P15), or if a plurality of requesting master devices (3-1, . . . 3-N) have the same highest priority value (P0, . . . P15): access to the respective slave devices (4-1, . . . 4-M) is successively granted to the requesting master devices (3-1, . . . 3-N) which have the highest priority value (P0, . . . P15) on the basis of the address allocation of the master devices (3-1, . . . 3-N).
摘要翻译：一种用于在多主机总线系统（2）中分配总线访问权限的方法，具有以下步骤：将地址（MASTER 0-MASTER 15）明确地分配给多主机中的主设备（3 -1，... 3 -N）总线系统，从优先级值（P 0 ... P 15）的组织优先级列表（5）中分配优先级值（P 0，...，P 15）到每个主设备（3 - 1，...， 3 -N），来自至少一个主设备（3-1，...，3-N）的请求使用总线系统（2）访问从设备（4-1），...，4-M），则比较所有请求主设备（3 -1，... 3 -N）的优先级值（P 0，...，P 15），如果唯一请求主设备（3 - 1，... 3 -N）具有最高优先级值（P 0，...，P 15）：对相应从属设备（4 - 1，...，4 -M）的唯一访问权限被授予具有最高优先级值（P 0，...，P 15）的请求主设备（3 -1，... 3 -N），或者多个请求主设备（3-1，。。 3-N）具有相同的最高优先级值（P 0，...，P 15）：对相应从属设备（4-1，...，4M）的访问被连续授予请求主设备（3 - 1，... 3 -N），其中优先权值（P 0，...，P 15）优先级高于主设备（3 - 1，... 3 -N）的地址分配。

7. 发明申请

US20050157586A1 Arrangement comprising a memory device and a program-controlled unit 有权
标题翻译：布置包括存储器件和程序控制单元
公开(公告)号：US20050157586A1
公开(公告)日：2005-07-21
申请号：US11018327
申请日：2004-12-21
申请人： Ernst Kock , Frank Hellwig
发明人： Ernst Kock , Frank Hellwig
IPC分类号： G06F13/12 , G11C7/22 , G11C8/00 , G11C11/4076
CPC分类号： G11C11/4076 , G11C7/1066 , G11C7/22 , G11C7/222
摘要： An arrangement comprises a memory device for storing data, and a program-controlled unit with a memory interface for reading data out of the memory device. The memory device is supplied with a first clock signal and transmits the data at the rate of a second clock signal, and the second clock signal to the memory interface when the memory interface performs a read access. The first clock signal is also supplied to the memory interface which generates from this signal a third clock signal which has the same frequency as the first and second clock signal but a predetermined phase shift with respect to the second clock signal. The memory interface accepts the data with the rising and/or falling edges of the third clock signal or the inverted third clock signal, and the third clock signal is also used as clock signal by other components of the memory interface.
摘要翻译：一种装置包括用于存储数据的存储装置，以及具有用于从存储装置读出数据的存储器接口的程序控制单元。当存储器接口执行读取访问时，存储器件被提供有第一时钟信号并以第二时钟信号的速率传输数据，并且将第二时钟信号发送到存储器接口。第一时钟信号也被提供给从该信号产生具有与第一和第二时钟信号相同频率但相对于第二时钟信号的预定相移的第三时钟信号的存储器接口。存储器接口接收具有第三时钟信号或反相第三时钟信号的上升沿和/或下降沿的数据，并且第三时钟信号也被存储器接口的其他部件用作时钟信号。

8. 发明申请

US20050018528A1 Memory arrangement for processing data, and method 有权
标题翻译：用于处理数据的内存安排和方法
公开(公告)号：US20050018528A1
公开(公告)日：2005-01-27
申请号：US10878172
申请日：2004-06-28
申请人： Frank Hellwig
发明人： Frank Hellwig
IPC分类号： G11C7/22 , G11C11/4076 , G11C13/00
CPC分类号： G11C7/222 , G11C7/22 , G11C11/4076
摘要： The invention relates to a memory arrangement for processing data and to a method for operating this memory arrangement. The inventive method involves a control signal being transferred together with the data on, with a change in the control signal activating the DLL circuit and synchronizing it to a clock. In this case, the DLL circuit stipulates a sampling time for the data. In line with the invention, after a predetermined length of time within which no data have been read from the memory, the memory is accessed artificially in order to generate a change in the control signal for the DLL circuit.
摘要翻译：本发明涉及一种用于处理数据的存储装置和一种用于操作该存储装置的方法。本发明的方法涉及控制信号与数据一起转移，控制信号的变化激活DLL电路并将其同步到时钟。在这种情况下，DLL电路规定了数据的采样时间。根据本发明，在没有从存储器读取数据的预定时间长度之后，人为地访问存储器以便产生用于DLL电路的控制信号的改变。

9. 发明申请

US20110289377A1 SYSTEMS AND METHODS FOR SECURE INTERRUPT HANDLING 有权
标题翻译：用于安全中断处理的系统和方法
公开(公告)号：US20110289377A1
公开(公告)日：2011-11-24
申请号：US12784015
申请日：2010-05-20
申请人： Frank Hellwig , Antonio Vilela
发明人： Frank Hellwig , Antonio Vilela
IPC分类号： G06F11/08 , G06F13/26
CPC分类号： G06F13/26
摘要： The invention relates to systems for secure interrupt handling, a method for verifying a priority of a winning service request node and a method and an apparatus for verifying integrity of service requests.In accordance with an aspect of the invention, there is provided a method for verifying a priority of a winning service request node (SRN) established in an arbitration between a plurality of service request nodes (SRNs) performed by an interrupt controller, the method comprising: storing the priority of the winning SRN in the interrupt controller; encoding the priority of the winning SRN, wherein the encoding allows for error detection; transmitting the encoded priority from the winning SRN to the interrupt controller; and verifying the priority of the winning SRN by comparing the encoded priority transmitted by the winning SRN with the priority of the winning SRN established in the arbitration and stored in the interrupt controller.
摘要翻译：本发明涉及用于安全中断处理的系统，用于验证获胜服务请求节点的优先级的方法以及用于验证服务请求的完整性的方法和装置。根据本发明的一个方面，提供了一种用于验证在由中断控制器执行的多个服务请求节点（SRN）之间的仲裁中建立的获胜服务请求节点（SRN）的优先级的方法，所述方法包括：：将获胜的SRN的优先级存储在中断控制器中; 编码获胜SRN的优先级，其中编码允许错误检测; 将所述编码优先级从所述获胜SRN发送到所述中断控制器; 以及通过将获胜的SRN发送的编码优先级与在仲裁中建立并存储在中断控制器中的获胜SRN的优先级进行比较来验证获胜SRN的优先级。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式