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1. 发明授权

US07679164B2 Bipolar transistor with silicided sub-collector 有权
标题翻译：双极晶体管，带硅化子集电极
公开(公告)号：US07679164B2
公开(公告)日：2010-03-16
申请号：US11620242
申请日：2007-01-05
申请人： Francois Pagette , Christian Lavoie , Anna Topol
发明人： Francois Pagette , Christian Lavoie , Anna Topol
IPC分类号： H01L27/102
CPC分类号： H01L29/737 , H01L29/0821 , H01L29/66242
摘要： Embodiments of the invention provide a semiconductor device including a collector in an active region; a first and a second sub-collector, the first sub-collector being a heavily doped semiconductor material adjacent to the collector and the second sub-collector being a silicided sub-collector next to the first sub-collector; and a silicided reach-through in contact with the second sub-collector, wherein the first and second sub-collectors and the silicided reach-through provide a continuous conductive pathway for electrical charges collected by the collector from the active region. Embodiments of the invention also provide methods of fabricating the same.
摘要翻译：本发明的实施例提供了一种在有源区域中包括集电极的半导体器件; 第一和第二子集电极，所述第一子集电极是与所述集电极相邻的重掺杂半导体材料，所述第二子集电极是靠近所述第一子集电极的硅化副集电极; 以及与所述第二子集电器接触的硅化物到达通道，其中所述第一和第二子集电极和所述硅化物到达通道为所述集电器从所述有源区域收集的电荷提供连续的导电路径。本发明的实施例还提供了制造该方法的方法。

2. 发明申请

US20100003800A1 BIPOLAR TRANSISTOR WITH SILICIDED SUB-COLLECTOR 有权
标题翻译：双极晶体管，带有硅分集电极
公开(公告)号：US20100003800A1
公开(公告)日：2010-01-07
申请号：US12557557
申请日：2009-09-11
申请人： Francois Pagette , Christian Lavoie , Anna Topol
发明人： Francois Pagette , Christian Lavoie , Anna Topol
IPC分类号： H01L21/331
CPC分类号： H01L29/737 , H01L29/0821 , H01L29/66242
摘要： Embodiments of the invention provide a method of fabricating a semiconductor device. The method includes defining a sub-collector region in a layer of doped semiconductor material; forming an active region, a dielectric region, and a reach-through region on top of the layer of doped semiconductor material with the dielectric region separating the active region from the reach-through region; and siliciding the reach-through region and a portion of the sub-collector region to form a partially silicided conductive pathway. A semiconductor device made thereby is also provided.
摘要翻译：本发明的实施例提供一种制造半导体器件的方法。该方法包括在掺杂半导体材料层中限定子集电极区; 在所述掺杂半导体材料层的顶部上形成有源区，电介质区和到达区，所述电介质区将所述有源区与所述覆盖区分离; 并且将通过区域和子集电极区域的一部分硅化以形成部分硅化物的导电路径。还提供了由此制成的半导体器件。

3. 发明申请

US20080164494A1 BIPOLAR TRANSISTOR WITH SILICIDED SUB-COLLECTOR 有权
标题翻译：双极晶体管，带有硅分集电极
公开(公告)号：US20080164494A1
公开(公告)日：2008-07-10
申请号：US11620242
申请日：2007-01-05
申请人： Francois Pagette , Christian Lavoie , Anna Topol
发明人： Francois Pagette , Christian Lavoie , Anna Topol
IPC分类号： H01L29/737 , H01L29/73 , H01L21/04
CPC分类号： H01L29/737 , H01L29/0821 , H01L29/66242
摘要： Embodiments of the invention provide a semiconductor device including a collector in an active region; a first and a second sub-collector, the first sub-collector being a heavily doped semiconductor material adjacent to the collector and the second sub-collector being a silicided sub-collector next to the first sub-collector; and a silicided reach-through in contact with the second sub-collector, wherein the first and second sub-collectors and the silicided reach-through provide a continuous conductive pathway for electrical charges collected by the collector from the active region. Embodiments of the invention also provide methods of fabricating the same.
摘要翻译：本发明的实施例提供了一种在有源区域中包括集电极的半导体器件; 第一和第二子集电极，所述第一子集电极是与所述集电极相邻的重掺杂半导体材料，所述第二子集电极是靠近所述第一子集电极的硅化副集电极; 以及与所述第二子集电器接触的硅化物到达通道，其中所述第一和第二子集电极和所述硅化物到达通道为所述集电器从所述有源区域收集的电荷提供连续的导电路径。本发明的实施例还提供了制造该方法的方法。

4. 发明申请

US20070218641A1 FULLY SILICIDED EXTRINSIC BASE TRANSISTOR 失效
标题翻译：完全硅酸超级基极晶体管
公开(公告)号：US20070218641A1
公开(公告)日：2007-09-20
申请号：US11308259
申请日：2006-03-14
申请人： David Ahlgren , Guy Cohen , Christian Lavoie , Francois Pagette , Anna Topol
发明人： David Ahlgren , Guy Cohen , Christian Lavoie , Francois Pagette , Anna Topol
IPC分类号： H01L21/331 , H01L21/8222
CPC分类号： H01L29/1004 , H01L29/1608 , H01L29/66242 , H01L29/66287 , H01L29/732 , H01L29/7378
摘要： A system and method comprises forming an intrinsic base on a collector. The system and method further includes forming a fully silicided extrinsic base on the intrinsic base by a self-limiting silicidation process at a predetermined temperature and for a predetermined amount of time, the silicidation substantially stopping at the intrinsic base. The system and method further includes forming an emitter which is physically insulated from the extrinsic base and the collector, and which is in physical contact with the intrinsic base.
摘要翻译：一种系统和方法包括在收集器上形成固有碱基。该系统和方法还包括通过在预定温度下的自限硅化工艺在本征基底上形成完全硅化的外在碱，并且预定量的时间，硅化物在本征碱基本上停止。该系统和方法还包括形成与外部基极和集电器物理绝缘的发射极，并与内部基极物理接触。

5. 发明授权

US08003473B2 Bipolar transistor with silicided sub-collector 有权
标题翻译：双极晶体管，带硅化子集电极
公开(公告)号：US08003473B2
公开(公告)日：2011-08-23
申请号：US12557557
申请日：2009-09-11
申请人： Francois Pagette , Christian Lavoie , Anna Topol
发明人： Francois Pagette , Christian Lavoie , Anna Topol
IPC分类号： H01L21/331
CPC分类号： H01L29/737 , H01L29/0821 , H01L29/66242
摘要： Embodiments of the invention provide a method of fabricating a semiconductor device. The method includes defining a sub-collector region in a layer of doped semiconductor material; forming an active region, a dielectric region, and a reach-through region on top of the layer of doped semiconductor material with the dielectric region separating the active region from the reach-through region; and siliciding the reach-through region and a portion of the sub-collector region to form a partially silicided conductive pathway. A semiconductor device made thereby is also provided.
摘要翻译：本发明的实施例提供一种制造半导体器件的方法。该方法包括在掺杂半导体材料层中限定子集电极区; 在所述掺杂半导体材料层的顶部上形成有源区，电介质区和到达区，所述电介质区将所述有源区与所述覆盖区分离; 并且将通过区域和子集电极区域的一部分硅化以形成部分硅化的导电路径。还提供了由此制成的半导体器件。

6. 发明申请

US20090026623A1 BURIED METAL-SEMICONDUCTOR ALLOY LAYERS AND STRUCTURES AND METHODS FOR FABRICATION THEREOF 有权
标题翻译：金属半导体合金层及其制造方法及其制造方法
公开(公告)号：US20090026623A1
公开(公告)日：2009-01-29
申请号：US11828455
申请日：2007-07-26
申请人： Christian Lavoie , Francois Pagette , Anna W. Topol
发明人： Christian Lavoie , Francois Pagette , Anna W. Topol
IPC分类号： H01L23/48 , H01L21/4763
CPC分类号： H01L23/53271 , H01L21/743 , H01L21/76243 , H01L21/76889 , H01L21/84 , H01L23/535 , H01L27/1203 , H01L29/78603 , H01L2924/0002 , H01L2924/00
摘要： A method for forming a metal-semiconductor alloy layer uses particular thermal annealing conditions to provide a stress free metal-semiconductor alloy layer through interdiffusion of a buried semiconductor material layer and a metal-semiconductor alloy forming metal layer that contacts the buried semiconductor material layer within an aperture through a capping layer beneath which is buried the semiconductor material layer. A resulting semiconductor structure includes the metal-semiconductor alloy layer that further includes an interconnect portion beneath the capping layer and a contiguous via portion that penetrates at least partially through the capping layer. Such a metal-semiconductor alloy layer may be located interposed between a substrate and a semiconductor device having an active doped region.
摘要翻译：一种形成金属 - 半导体合金层的方法使用特定的热退火条件，通过掩埋半导体材料层和接触掩埋半导体材料层的金属 - 半导体合金形成金属层的相互扩散来提供无应力的金属 - 半导体合金层，穿过覆盖层的孔，其下埋有半导体材料层。所得到的半导体结构包括还包括覆盖层下面的互连部分的金属 - 半导体合金层和至少部分地穿过覆盖层的连续通孔部分。这种金属 - 半导体合金层可以位于衬底和具有有源掺杂区域的半导体器件之间。

7. 发明授权

US08791572B2 Buried metal-semiconductor alloy layers and structures and methods for fabrication thereof 有权
公开(公告)号：US08791572B2
公开(公告)日：2014-07-29
申请号：US11828455
申请日：2007-07-26
申请人： Christian Lavoie , Francois Pagette , Anna W. Topol
发明人： Christian Lavoie , Francois Pagette , Anna W. Topol
IPC分类号： H01L23/48 , H01L21/4763
CPC分类号： H01L23/53271 , H01L21/743 , H01L21/76243 , H01L21/76889 , H01L21/84 , H01L23/535 , H01L27/1203 , H01L29/78603 , H01L2924/0002 , H01L2924/00
摘要： A method for forming a metal-semiconductor alloy layer uses particular thermal annealing conditions to provide a stress free metal-semiconductor alloy layer through interdiffusion of a buried semiconductor material layer and a metal-semiconductor alloy forming metal layer that contacts the buried semiconductor material layer within an aperture through a capping layer beneath which is buried the semiconductor material layer. A resulting semiconductor structure includes the metal-semiconductor alloy layer that further includes an interconnect portion beneath the capping layer and a contiguous via portion that penetrates at least partially through the capping layer. Such a metal-semiconductor alloy layer may be located interposed between a substrate and a semiconductor device having an active doped region.

8. 发明授权

US08759213B2 Buried metal-semiconductor alloy layers and structures and methods for fabrication thereof 有权
标题翻译：埋地金属 - 半导体合金层及其制造方法及其制造方法
公开(公告)号：US08759213B2
公开(公告)日：2014-06-24
申请号：US13607869
申请日：2012-09-10
申请人： Christian Lavoie , Francois Pagette , Anna W. Topol
发明人： Christian Lavoie , Francois Pagette , Anna W. Topol
IPC分类号： H01L21/4763
CPC分类号： H01L23/53271 , H01L21/743 , H01L21/76243 , H01L21/76889 , H01L21/84 , H01L23/535 , H01L27/1203 , H01L29/78603 , H01L2924/0002 , H01L2924/00
摘要： A method for forming a metal-semiconductor alloy layer uses particular thermal annealing conditions to provide a stress free metal-semiconductor alloy layer through interdiffusion of a buried semiconductor material layer and a metal-semiconductor alloy forming metal layer that contacts the buried semiconductor material layer within an aperture through a capping layer beneath which is buried the semiconductor material layer. A resulting semiconductor structure includes the metal-semiconductor alloy layer that further includes an interconnect portion beneath the capping layer and a contiguous via portion that penetrates at least partially through the capping layer. Such a metal-semiconductor alloy layer may be located interposed between a substrate and a semiconductor device having an active doped region.
摘要翻译：一种形成金属 - 半导体合金层的方法使用特定的热退火条件，通过掩埋半导体材料层和接触掩埋半导体材料层的金属 - 半导体合金形成金属层的相互扩散来提供无应力的金属 - 半导体合金层，穿过覆盖层的孔，其下埋有半导体材料层。所得到的半导体结构包括还包括覆盖层下面的互连部分的金属 - 半导体合金层和至少部分地穿过覆盖层的连续通孔部分。这种金属 - 半导体合金层可以位于衬底和具有有源掺杂区域的半导体器件之间。

9. 发明申请

US20120326318A1 BURIED METAL-SEMICONDUCTOR ALLOY LAYERS AND STRUCTURES AND METHODS FOR FABRICATION THEREOF 有权
标题翻译：金属半导体合金层及其制造方法及其制造方法
公开(公告)号：US20120326318A1
公开(公告)日：2012-12-27
申请号：US13607869
申请日：2012-09-10
申请人： Christian Lavoie , Francois Pagette , Anna W. Topol
发明人： Christian Lavoie , Francois Pagette , Anna W. Topol
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L23/53271 , H01L21/743 , H01L21/76243 , H01L21/76889 , H01L21/84 , H01L23/535 , H01L27/1203 , H01L29/78603 , H01L2924/0002 , H01L2924/00
摘要： A method for forming a metal-semiconductor alloy layer uses particular thermal annealing conditions to provide a stress free metal-semiconductor alloy layer through interdiffusion of a buried semiconductor material layer and a metal-semiconductor alloy forming metal layer that contacts the buried semiconductor material layer within an aperture through a capping layer beneath which is buried the semiconductor material layer. A resulting semiconductor structure includes the metal-semiconductor alloy layer that further includes an interconnect portion beneath the capping layer and a contiguous via portion that penetrates at least partially through the capping layer. Such a metal-semiconductor alloy layer may be located interposed between a substrate and a semiconductor device having an active doped region.
摘要翻译：一种形成金属 - 半导体合金层的方法使用特定的热退火条件，通过掩埋半导体材料层和接触掩埋半导体材料层的金属 - 半导体合金形成金属层的相互扩散来提供无应力的金属 - 半导体合金层，穿过覆盖层的孔，其下埋有半导体材料层。所得到的半导体结构包括还包括覆盖层下面的互连部分的金属 - 半导体合金层和至少部分地穿过覆盖层的连续通孔部分。这种金属 - 半导体合金层可以位于衬底和具有有源掺杂区域的半导体器件之间。

10. 发明授权

US07585740B2 Fully silicided extrinsic base transistor 失效
标题翻译：全硅化外基晶体管
公开(公告)号：US07585740B2
公开(公告)日：2009-09-08
申请号：US11308259
申请日：2006-03-14
申请人： David C. Ahlgren , Guy M. Cohen , Christian Lavoie , Francois Pagette , Anna W. Topol
发明人： David C. Ahlgren , Guy M. Cohen , Christian Lavoie , Francois Pagette , Anna W. Topol
IPC分类号： H01L21/331
CPC分类号： H01L29/1004 , H01L29/1608 , H01L29/66242 , H01L29/66287 , H01L29/732 , H01L29/7378
摘要： A system and method comprises forming an intrinsic base on a collector. The system and method further includes forming a fully silicided extrinsic base on the intrinsic base by a self-limiting silicidation process at a predetermined temperature and for a predetermined amount of time, the silicidation substantially stopping at the intrinsic base. The system and method further includes forming an emitter which is physically insulated from the extrinsic base and the collector, and which is in physical contact with the intrinsic base.
摘要翻译：一种系统和方法包括在收集器上形成固有碱基。该系统和方法还包括通过在预定温度下的自限硅化工艺在本征基底上形成完全硅化的外在碱，并且预定量的时间，硅化物在本征碱基本上停止。该系统和方法还包括形成与外部基极和集电器物理绝缘的发射极，并与内部基极物理接触。

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