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1. 发明授权

US06872665B1 Process flow for dual damescene interconnect structures 有权
标题翻译：双重二连体互连结构的工艺流程
公开(公告)号：US06872665B1
公开(公告)日：2005-03-29
申请号：US09599718
申请日：2000-06-22
申请人： Francis G. Celii , Guoqiang Xing , Andrew McKerrow , Andrew Ralston , Zhicheng Tang , Kenneth J. Newton , Robert Kraft , Jeff West
发明人： Francis G. Celii , Guoqiang Xing , Andrew McKerrow , Andrew Ralston , Zhicheng Tang , Kenneth J. Newton , Robert Kraft , Jeff West
IPC分类号： H01L21/768 , H01L21/20
CPC分类号： H01L21/76808
摘要： A dual damascene process flow for forming interconnect lines and vias in which at least part of the via (116) is etched prior to the trench etch. A low-k material such as a thermoset organic polymer is used for the ILD (106) and IMD (110). After the at least partial via etch, a BARC (120) is deposited over the structure including in the via (116). Then, the trench (126) is patterned and etched. Although at least some of the BARC (120) material is removed during the trench etch, the bottom of the via (116) is protected.
摘要翻译：用于形成互连线和通孔的双镶嵌工艺流程，其中在沟槽蚀刻之前蚀刻至少部分通孔（116）。使用低k材料如热固性有机聚合物用于ILD（106）和IMD（110）。在至少部分通孔蚀刻之后，BARC（120）沉积在包括在通孔（116）中的结构上。然后，对沟槽（126）进行图案化和蚀刻。虽然在沟槽蚀刻期间去除了至少一些BARC（120）材料，但是通孔（116）的底部被保护。

2. 发明授权

US06455411B1 Defect and etch rate control in trench etch for dual damascene patterning of low-k dielectrics 有权
标题翻译：对于低k电介质的双镶嵌图案，沟槽蚀刻中的缺陷和蚀刻速率控制
公开(公告)号：US06455411B1
公开(公告)日：2002-09-24
申请号：US09947966
申请日：2001-09-06
申请人： Ping Jiang , Francis G. Celii , Kenneth J. Newton , Hiromi Sakima
发明人： Ping Jiang , Francis G. Celii , Kenneth J. Newton , Hiromi Sakima
IPC分类号： H01L21308
CPC分类号： H01L21/76808 , H01L21/31116 , H01L21/31138 , H01L21/31144
摘要： A dual damascene process for low-k or ultra low-k dielectric such as organo-silicate glass (OSG). After the via (112) etch, a trench (121) is etched in the OSG layer (108) using a less-polymerizing fluorocarbon added to an etch chemistry comprising a fluorocarbon and low N2/Ar ratio. The low N2/Ar ratio controls ridge formation during the trench etch. The combination of a less-polymerizing fluorocarbon with a higher-polymerizing fluorocarbon achieves a high etch rate and defect-free conditions.
摘要翻译：用于低k或超低k电介质的双镶嵌工艺，如有机硅酸盐玻璃（OSG）。在通孔（112）蚀刻之后，使用添加到包含碳氟化合物和低N 2 / Ar比的蚀刻化学品中的较少聚合的碳氟化合物在OSG层（108）中蚀刻沟槽（121）。低N 2 / Ar比控制沟槽蚀刻期间的脊形成。低聚碳氟化合物与较高聚合碳氟化合物的组合实现了高蚀刻速率和无缺陷条件。

3. 发明授权

US07300883B2 Method for patterning sub-lithographic features in semiconductor manufacturing 有权
标题翻译：在半导体制造中图案化亚光刻特征的方法
公开(公告)号：US07300883B2
公开(公告)日：2007-11-27
申请号：US10930228
申请日：2004-08-31
申请人： Francis G. Celii , Brian A. Smith , James Blatchford , Robert Kraft
发明人： Francis G. Celii , Brian A. Smith , James Blatchford , Robert Kraft
IPC分类号： H01L21/336 , H01L21/302 , H01L21/461 , H01L21/31 , H01L21/469
CPC分类号： H01L21/28123 , H01L21/0337 , H01L21/0338 , H01L21/32139
摘要： A method of forming a gate electrode (24′) for a metal-oxide-semiconductor (MOS) integrated circuit is disclosed. A hardmask layer (26), for example formed of silicon-rich nitride, is deposited over a polysilicon layer (24) from which the gate electrode (24′) is to be formed. An anti-reflective coating, or bottom anti-reflective coating or BARC, layer (29) is then formed over the hardmask layer (26), and photoresist (30) is photolithographically patterned to define the pattern of the gate electrode (24′), although to a wider, photolithographic, width (LW). The pattern is transferred from the photoresist (30) to the BARC layer (29). The remaining elements of the BARC layer (29) are then trimmed, preferably by a timed isotropic etch, to a sub-lithographic width (SW). This pattern is then transferred to the hardmask layer (26) by an anisotropic etch of that layer, using the trimmed BARC elements (29) as a mask. The hardmask layer elements (26′) then mask the etch of the underlying polysilicon layer (24), to define the gate electrodes (24′), having gate widths that are narrower than the minimum dimension available through photolithography.
摘要翻译：公开了一种形成用于金属氧化物半导体（MOS）集成电路的栅电极（24'）的方法。例如由富含硅的氮化物形成的硬掩模层（26）沉积在要形成栅电极（24'）的多晶硅层（24）上。然后在硬掩模层（26）上形成抗反射涂层或底部抗反射涂层或BARC层（29），光刻图案化光致抗蚀剂（30）以限定栅电极（24'）的图案，，尽管对于更宽的光刻宽度（LW）。图案从光致抗蚀剂（30）转移到BARC层（29）。然后将BARC层（29）的其余元件优选地通过定时各向同性蚀刻修整到亚光刻宽度（SW）。然后通过该层的各向异性蚀刻，使用修剪的BARC元件（29）作为掩模将该图案转移到硬掩模层（26）。硬掩模层元件（26'）然后掩蔽下面的多晶硅层（24）的蚀刻，以限定栅电极（24'），栅极宽度比通过光刻可用的最小尺寸窄。

4. 发明申请

US20070281422A1 Mitigation of edge degradation in ferroelectric memory devices through plasma etch clean 有权
标题翻译：通过等离子体蚀刻清洁减轻铁电存储器件中的边缘退化
公开(公告)号：US20070281422A1
公开(公告)日：2007-12-06
申请号：US11442810
申请日：2006-05-30
申请人： Kezhakkedath R. Udayakumar , Lindsey H. Hall , Francis G. Celii , Scott R. Summerfelt
发明人： Kezhakkedath R. Udayakumar , Lindsey H. Hall , Francis G. Celii , Scott R. Summerfelt
IPC分类号： H01L21/336
CPC分类号： H01L21/31122 , H01L21/0206 , H01L21/02071 , H01L21/32136 , H01L27/11502 , H01L28/55 , H01L28/65
摘要： A ferroelectric memory device is fabricated while mitigating edge degradation. A bottom electrode is formed over one or more semiconductor layers. A ferroelectric layer is formed over the bottom electrode. A top electrode is formed over the ferroelectric layer. The top electrode, the ferroelectric layer, and the bottom electrode are patterned or etched. A dry clean is performed that mitigates edge degradation. A wet etch/clean is then performed.
摘要翻译：制造铁电存储器件，同时减轻边缘退化。在一个或多个半导体层上形成底部电极。在底部电极上形成铁电层。顶部电极形成在铁电层上。上电极，铁电层和底电极被图案化或蚀刻。进行干洗以减轻边缘退化。然后进行湿蚀刻/清洁。

5. 发明授权

US5956148A Semiconductor surface measurement system and method 失效
标题翻译：半导体表面测量系统及方法
公开(公告)号：US5956148A
公开(公告)日：1999-09-21
申请号：US989904
申请日：1997-12-12
申请人： Francis G. Celii
发明人： Francis G. Celii
IPC分类号： G01B11/06 , G01J4/00
CPC分类号： G01B11/0641
摘要： A semiconductor surface measurement system (100) is disclosed. In this system, a plurality of wafers (106), each having an exposed surface, are held by a wafer positioning system (104), which sequentially moves the wafers into a measurement zone. A wafer position detection system (124) detects the position of a selected wafer, and generates an output signal indicating the position of the selected wafer. A surface measurement apparatus (114 through 121, 130 through 142) measures a property of the exposed surface of the selected wafer (106) in response to the output signal of the wafer position detection system (124) when the selected wafer is in the measurement zone. The disclosed surface measurement system (100)may be used to gather real-time data concerning surface properties such as composition, roughness and epilayer thickness during multi-wafer semiconductor processing.
摘要翻译：公开了半导体表面测量系统（100）。在该系统中，每个具有暴露表面的多个晶片（106）由晶片定位系统（104）保持，晶片定位系统（104）将晶片顺序地移动到测量区域中。晶片位置检测系统（124）检测所选晶片的位置，并产生指示所选晶片的位置的输出信号。当所选晶片处于测量状态时，表面测量装置（114至121,130至142）响应于晶片位置检测系统（124）的输出信号测量所选晶片（106）的暴露表面的性质区。公开的表面测量系统（100）可以用于收集关于多晶片半导体处理期间的表面特性（例如组成，粗糙度和外延层厚度）的实时数据。

6. 发明授权

US5756375A Semiconductor growth method with thickness control 失效
标题翻译：具有厚度控制的半导体生长方法
公开(公告)号：US5756375A
公开(公告)日：1998-05-26
申请号：US664940
申请日：1996-06-14
申请人： Francis G. Celii , Walter M. Duncan , Tae S. Kim
发明人： Francis G. Celii , Walter M. Duncan , Tae S. Kim
IPC分类号： H01L21/205 , H01L21/66 , H01L21/203
CPC分类号： B24B37/013 , H01L22/26 , H01L21/02392 , H01L21/02463 , H01L21/02546
摘要： Molecular beam epitaxy (202) with growing layer thickness and doping control (206) by feedback of sensor signals such as spectrosceopic ellipsometer signals based on a process model. Examples include III-V compound structures with multiple AlAs, InGaAs, and InAs layers as used in resonant tunneling diodes and hetrojunction bipolar transistors with doped and undoped GaAs layers, AlGaAs and InGaAs.
摘要翻译：通过基于过程模型的传感器信号（例如光谱椭偏仪信号）的反馈，分子束外延（202）具有增长的层厚度和掺杂控制（206）。实例包括具有多个AlAs，InGaAs和InAs层的III-V化合物结构，其用于具有掺杂和未掺杂的GaAs层，AlGaAs和InGaAs的谐振隧道二极管和掺杂双极晶体管。

7. 发明授权

US5556462A Growth method by repeatedly measuring flux in MBE chamber 失效
标题翻译：通过重复测量MBE室中的通量的生长方法
公开(公告)号：US5556462A
公开(公告)日：1996-09-17
申请号：US349713
申请日：1994-12-05
申请人： Francis G. Celii , Yung-Chung Kao , Andrew J. Purdes
发明人： Francis G. Celii , Yung-Chung Kao , Andrew J. Purdes
IPC分类号： C30B25/02 , C23C14/22 , C30B23/02 , C30B23/08 , H01L21/203 , H01L21/331 , H01L21/66 , H01L29/205 , H01L29/73 , H01L29/737 , C30B23/00
CPC分类号： H01L22/26 , B24B37/013 , B82Y10/00 , B82Y15/00 , C30B23/002 , C30B29/40
摘要： Molecular beam epitaxy (202) with growing layer thickness control (206) by feedback of integrated mass spectormeter (204) signals. Examples include III-V compound structures with multiple AlAs, InGaAs, and InAs layers as used in resonant tunneling diodes.
摘要翻译：分子束外延（202）通过集成质谱仪（204）信号的反馈而增长层厚度控制（206）。实例包括具有多个AlAs，InGaAs和InAs层的III-V族化合物结构，如共振隧道二极管所用。

8. 发明授权

US5082522A Method for forming patterned diamond thin films 失效
标题翻译：用于形成图案化金刚石薄膜的方法
公开(公告)号：US5082522A
公开(公告)日：1992-01-21
申请号：US567423
申请日：1990-08-14
申请人： Andrew J. Purdes , Francis G. Celii
发明人： Andrew J. Purdes , Francis G. Celii
IPC分类号： C30B25/02 , C30B25/04 , H01L21/20 , H01L21/314 , H01L21/768 , H01L23/532
CPC分类号： H01L23/5329 , C30B25/02 , C30B25/04 , C30B29/04 , H01L21/02381 , H01L21/02425 , H01L21/02444 , H01L21/02527 , H01L21/0262 , H01L21/02639 , H01L21/3146 , H01L21/76801 , H01L2924/0002
摘要： Preferred embodiments mask select regions of a circuit surface (141) prior to abrading the surface with diamond particles to form nucleation sites (200). The mask (150) is then removed prior to forming a diamond layer (160). Diamond layer (160) grows on the surface except in those regions wherein the mask (150) prevented the formation of nucleation sites (200).
摘要翻译：优选实施例在用金刚石颗粒研磨表面以形成成核位点（200）之前掩蔽电路表面（141）的选择区域。然后在形成金刚石层（160）之前去除掩模（150）。金刚石层（160）在表面上生长，除了掩模（150）防止形成成核位点（200）的那些区域之外。

9. 发明授权

US07560385B2 Etching systems and processing gas specie modulation 有权
标题翻译：蚀刻系统和加工气体调制
公开(公告)号：US07560385B2
公开(公告)日：2009-07-14
申请号：US10263981
申请日：2002-10-03
申请人： Francis G. Celii , Ping Jiang
发明人： Francis G. Celii , Ping Jiang
IPC分类号： H01L21/302
CPC分类号： H01L21/31116
摘要： A method and system for etching a substrate control selectivity of the etch process by modulating the gas specie of the reactants. The gas specie selectively form and etch a buffer layer that protects underlying etch stop materials thereby providing highly selective etch processes.
摘要翻译：用于通过调节反应物的气体样品蚀刻蚀刻工艺的衬底控制选择性的方法和系统。气体选择性地形成和蚀刻缓冲层，其保护潜在的蚀刻停止材料，从而提供高度选择性的蚀刻工艺。

10. 发明申请

US20080303141A1 METHOD FOR ETCHING A SUBSTRATE AND A DEVICE FORMED USING THE METHOD 审中-公开
标题翻译：用于蚀刻基板的方法和使用该方法形成的器件
公开(公告)号：US20080303141A1
公开(公告)日：2008-12-11
申请号：US12137692
申请日：2008-06-12
申请人： K.R. Udayakumar , Ted S. Moise , Scott R. Summerfelt , Martin G. Albrecht , William W. Dostalik, JR. , Francis G. Celii
发明人： K.R. Udayakumar , Ted S. Moise , Scott R. Summerfelt , Martin G. Albrecht , William W. Dostalik, JR. , Francis G. Celii
IPC分类号： H01L23/535
CPC分类号： H01L21/31116 , H01L21/31616 , H01L21/76895 , H01L28/55
摘要： The present invention provides a method for etching a substrate, a method for forming an integrated circuit, an integrated circuit formed using the method, and an integrated circuit. The method for etching a substrate includes, among other steps, providing a substrate 140 having an aluminum oxide etch stop layer 130 located thereunder, and then etching an opening 150, 155, in the substrate 140 using an etchant comprising carbon oxide, a fluorocarbon, an etch rate modulator, and an inert carrier gas, wherein a flow rate of the carbon oxide is greater than about 80 sccm and the etchant is selective to the aluminum oxide etch stop layer 130. The aluminum oxide etch stop layer may also be used in the back-end of advanced CMOS processes as a via etch stop layer.
摘要翻译：本发明提供了蚀刻基板的方法，集成电路的形成方法，使用该方法形成的集成电路和集成电路。除了其它步骤之外，用于蚀刻衬底的方法包括提供具有位于其下方的氧化铝蚀刻停止层130的衬底140，然后使用包含碳氧化物，碳氟化合物的蚀刻剂在衬底140中蚀刻开口150,155，蚀刻速率调制器和惰性载气，其中碳氧化物的流速大于约80sccm，蚀刻剂对氧化铝蚀刻停止层130是选择性的。氧化铝蚀刻停止层也可以用于高级CMOS工艺的后端作为通孔蚀刻停止层。

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