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1. 发明授权

US6087881A Integrated circuit dual level shift predrive circuit 失效
标题翻译：集成电路双电平偏移预驱动电路
公开(公告)号：US6087881A
公开(公告)日：2000-07-11
申请号：US121515
申请日：1998-07-23
申请人： Francis Chan , Jeffrey H. Sloan , Douglas W. Stout
发明人： Francis Chan , Jeffrey H. Sloan , Douglas W. Stout
IPC分类号： H03K19/003 , H03L5/00
CPC分类号： H03K19/00315
摘要： A dual stage voltage level predrive circuit for an integrated circuit chip including two level shifter stages in series. The voltage level shifting circuit uses single dielectric layer devices and three bias supply circuits each providing a different DC bias voltage for distributing bias voltages among the devices such that dielectric voltage stress across single dielectric layers is reduced. The first stage of the level shifting circuit receives a first input signal having a first voltage swing, converts the first voltage swing to a second voltage swing and provides a first output signal corresponding to the first input signal and having the second voltage swing. The second stage of the level shifting circuit receives the first output signal from the first stage, converts the second voltage swing to a third voltage swing and provides a final output signal having the third voltage swing.
摘要翻译：一种用于集成电路芯片的双级电压电平预调制电路，包括两个电平转换级串联。电压电平移位电路使用单个电介质层器件和三个偏置电源电路，每个偏置电源电路提供不同的直流偏置电压，用于在器件之间分配偏置电压，从而降低跨单个电介质层的介电电压应力。电平移位电路的第一级接收具有第一电压摆幅的第一输入信号，将第一电压摆幅转换为第二电压摆幅，并提供对应于第一输入信号并具有第二电压摆幅的第一输出信号。电平移位电路的第二级接收来自第一级的第一输出信号，将第二电压摆幅转换为第三电压摆幅，并提供具有第三电压摆幅的最终输出信号。

2. 发明授权

US07348657B2 Electrostatic discharge protection networks for triple well semiconductor devices 有权
标题翻译：三阱半导体器件的静电放电保护网络
公开(公告)号：US07348657B2
公开(公告)日：2008-03-25
申请号：US11425491
申请日：2006-06-21
申请人： James P. Pequignot , Jeffrey H. Sloan , Douglas W. Stout , Steven H. Voldman
发明人： James P. Pequignot , Jeffrey H. Sloan , Douglas W. Stout , Steven H. Voldman
IPC分类号： H01L29/06
CPC分类号： H01L27/0255 , H01L2924/0002 , H01L2924/00
摘要： An electrostatic discharge protection network that uses triple well semiconductor devices either singularly or in a series configuration. The semiconductor devices are preferably in diode junction type configuration.
摘要翻译：一种使用三重阱半导体器件的静电放电保护网络，其单体或串联配置。半导体器件优选为二极管结型。

3. 发明授权

US06891207B2 Electrostatic discharge protection networks for triple well semiconductor devices 失效
标题翻译：三阱半导体器件的静电放电保护网络
公开(公告)号：US06891207B2
公开(公告)日：2005-05-10
申请号：US10248329
申请日：2003-01-09
申请人： James P. Pequignot , Jeffrey H. Sloan , Douglas W. Stout , Steven H. Voldman
发明人： James P. Pequignot , Jeffrey H. Sloan , Douglas W. Stout , Steven H. Voldman
IPC分类号： H01L21/761 , H01L21/822 , H01L21/8238 , H01L27/02 , H01L27/04 , H01L27/06 , H01L27/08 , H01L27/092 , H01L29/74 , H01L23/62
CPC分类号： H01L27/0255 , H01L27/0814 , H01L2924/0002 , H01L2924/00
摘要： An electrostatic discharge protection network that uses triple well semiconductor devices either singularly or in a series configuration. The semiconductor devices are preferably in diode junction type configuration. A control network can be used to control the biasing when the semiconductor devices are used in a series configuration.
摘要翻译：一种使用三重阱半导体器件的静电放电保护网络，其单体或串联配置。半导体器件优选为二极管结型。当半导体器件以串联配置使用时，可以使用控制网络来控制偏置。

4. 发明授权

US6157530A Method and apparatus for providing ESD protection 有权
标题翻译：提供ESD保护的方法和装置
公开(公告)号：US6157530A
公开(公告)日：2000-12-05
申请号：US224766
申请日：1999-01-04
申请人： James P. Pequignot , Tariq Rahman , Jeffrey H. Sloan , Douglas W. Stout , Steven H. Voldman
发明人： James P. Pequignot , Tariq Rahman , Jeffrey H. Sloan , Douglas W. Stout , Steven H. Voldman
IPC分类号： H01L27/02 , H02H3/22
CPC分类号： H01L27/0248
摘要： A novel ESD protection circuit for multiple power supplies, having both inventive inter-rail ESD circuitry and inventive single-rail ESD circuitry. The inter-rail ESD circuitry is scaleable and comprises one or more diode strings for interconnecting a pair of power rails. The ESD trigger voltage for a diode string is set by the number of diodes within the diode string and preferably a sufficient number of diodes are provided within each diode string for power-up and power-down sequence independence. The single-rail ESD circuitry is connected to a level-shifter and may comprise an RC discriminator comprising two NFET transistors connected in series. The RC discriminator may be connected to a clamping transistor via a buffering circuit, such as an inverter stage, that isolates the gate capacitance of the clamping transistor from the RC discriminator so that the RC characteristics of the RC discriminator are unaffected by the choice of the clamping transistor. The ESD protection circuit may be constructed from a selection from user-selectable discrete circuit elements formed on the chip.
摘要翻译：一种用于多个电源的新型ESD保护电路，具有本发明的轨间ESD电路和本发明的单轨ESD电路。轨间ESD电路是可扩展的，并且包括用于互连一对电源轨的一个或多个二极管串。二极管串的ESD触发电压由二极管串中的二极管的数量来设定，并且优选地，在每个二极管串内提供足够数量的二极管用于加电和断电顺序独立性。单轨ESD电路连接到电平移位器，并且可以包括RC鉴频器，其包括串联连接的两个NFET晶体管。 RC鉴频器可以经由诸如逆变器级的缓冲电路连接到钳位晶体管，其将钳位晶体管的栅极电容与RC鉴别器隔离，使得RC鉴别器的RC特性不受选择的影响钳位晶体管。 ESD保护电路可以由从芯片上形成的用户可选择的分立电路元件的选择构成。

5. 发明授权

US06292343B1 ASIC book to provide ESD protection on an integrated circuit 失效
标题翻译： ASIC集成电路为集成电路提供ESD保护
公开(公告)号：US06292343B1
公开(公告)日：2001-09-18
申请号：US09666632
申请日：2000-09-21
申请人： James P. Pequignot , Tariq Rahman , Jeffrey H. Sloan , Douglas W. Stout , Steven H. Voldman
发明人： James P. Pequignot , Tariq Rahman , Jeffrey H. Sloan , Douglas W. Stout , Steven H. Voldman
IPC分类号： H02H322
CPC分类号： H01L27/0248
摘要： An ASIC book comprising a gate-array format of ESD components is provided. A customized, optimized and tuned ESD network can be constructed from the ASIC book. Novel ESD circuitry having inter-rail ESD circuitry and single-rail ESD circuitry can be constructed. The inter-rail ESD circuitry is scaleable and comprises one or more diode strings for interconnecting a pair of power rails. The ESD trigger voltage for a diode string is set by the number of diodes within the customized diode string and preferably a sufficient number of diodes are provided within each diode string for power-up and power-down sequence independence. The single-rail ESD circuitry is connected to a level-shifter and may comprise an RC discriminator comprising a customizable plurality of NFET transistors connected in series. The RC discriminator may be connected to a clamping transistor via a buffering circuit, such as an inverter stage, that isolates the gate capacitance of the clamping transistor from the RC discriminator. In a second aspect of the invention an ASIC book comprising a gate-array format of ESD components is provided. A customized, optimized and tuned ESD network can be constructed from the ASIC book.
摘要翻译：提供了一种包括ESD组件的门阵列格式的ASIC书。可以通过ASIC书籍构建定制，优化和调优的ESD网络。可以构建具有轨间ESD电路和单轨ESD电路的新型ESD电路。轨间ESD电路是可扩展的，并且包括用于互连一对电源轨的一个或多个二极管串。二极管串的ESD触发电压由定制二极管串中的二极管的数量设定，并且优选地，在每个二极管串内提供足够数量的二极管用于上电和断电序列独立性。单轨ESD电路连接到电平转换器，并且可以包括RC鉴频器，RC鉴频器包括串联连接的可定制的多个NFET晶体管。 RC鉴频器可以经由缓冲电路（例如逆变器级）连接到钳位晶体管，该缓冲电路将钳位晶体管的栅极电容与RC鉴别器隔离。在本发明的第二方面，ASIC书籍包括栅极阵列提供了ESD组件的格式。可以通过ASIC书籍构建定制，优化和调优的ESD网络。

6. 发明授权

US06262873B1 Method for providing ESD protection for an integrated circuit 失效
标题翻译：为集成电路提供ESD保护的方法
公开(公告)号：US06262873B1
公开(公告)日：2001-07-17
申请号：US09657081
申请日：2000-09-07
申请人： James P. Pequignot , Tariq Rahman , Jeffrey H. Sloan , Douglas W. Stout , Steven H. Voldman
发明人： James P. Pequignot , Tariq Rahman , Jeffrey H. Sloan , Douglas W. Stout , Steven H. Voldman
IPC分类号： H02H322
CPC分类号： H01L27/0248
摘要： A method for automatically generating a custom ESD network for an integrated circuit is provided. When a user provides chip size and chip capacitance for the integrated circuit, components for the customized ESD network are automatically selected based on the user-provided chip size and chip capacitance and the adequacy of the ESD behavior of an ESD network employing the selected components is evaluated.
摘要翻译：提供了一种用于自动生成用于集成电路的定制ESD网络的方法。当用户为集成电路提供芯片尺寸和芯片电容时，根据用户提供的芯片尺寸和芯片电容自动选择定制ESD网络的组件，并且使用所选组件的ESD网络的ESD行为是否合适评估。

7. 发明授权

US07138701B2 Electrostatic discharge protection networks for triple well semiconductor devices 有权
标题翻译：三阱半导体器件的静电放电保护网络
公开(公告)号：US07138701B2
公开(公告)日：2006-11-21
申请号：US10605483
申请日：2003-10-02
申请人： James P. Pequignot , Jeffrey H. Sloan , Douglas W. Stout , Steven H. Voldman
发明人： James P. Pequignot , Jeffrey H. Sloan , Douglas W. Stout , Steven H. Voldman
IPC分类号： H01L29/00 , H01L23/62
CPC分类号： H01L27/0255 , H01L2924/0002 , H01L2924/00
摘要： An electrostatic discharge protection network that uses triple well semiconductor devices either singularly or in a series configuration. The semiconductor devices are preferably in diode junction type configuration.
摘要翻译：一种使用三重阱半导体器件的静电放电保护网络，其单体或串联配置。半导体器件优选为二极管结型。

8. 发明授权

US08486796B2 Thin film resistors and methods of manufacture 有权
标题翻译：薄膜电阻和制造方法
公开(公告)号：US08486796B2
公开(公告)日：2013-07-16
申请号：US12950635
申请日：2010-11-19
申请人： David L. Harmon , Joseph M. Lukaitis , Stewart E. Rauch, III , Robert R. Robison , Dustin K. Slisher , Jeffrey H. Sloan , Timothy D. Sullivan , Kimball M. Watson
发明人： David L. Harmon , Joseph M. Lukaitis , Stewart E. Rauch, III , Robert R. Robison , Dustin K. Slisher , Jeffrey H. Sloan , Timothy D. Sullivan , Kimball M. Watson
IPC分类号： H01L21/8222 , H01L23/62
CPC分类号： H01L23/5228 , H01L23/3677 , H01L23/5226 , H01L24/19 , H01L28/20 , H01L2224/04105 , H01L2224/73267 , H01L2924/14 , H01L2924/00
摘要： A method of forming a semiconductor structure includes: forming a resistor over a substrate; forming at least one first contact in contact with the resistor; and forming at least one second contact in contact with the resistor. The resistor is structured and arranged such that current flows from the at least one first contact to the at least one second contact through a central portion of the resistor. The resistor includes at least one extension extending laterally outward from the central portion in a direction parallel to the current flow. The method includes sizing the at least one extension based on a thermal diffusion length of the resistor.
摘要翻译：一种形成半导体结构的方法包括：在衬底上形成电阻器; 形成与所述电阻器接触的至少一个第一触点; 以及形成与所述电阻器接触的至少一个第二触点。电阻器被构造和布置成使得电流从电阻器的中心部分通过至少一个第一触点流到至少一个第二触点。该电阻器包括至少一个从平行于电流的方向从中心部分横向向外延伸的延伸部分。该方法包括基于电阻器的热扩散长度来确定至少一个延伸部的尺寸。

9. 发明申请

US20140184267A1 COMPENSATED IMPEDANCE CALIBRATION CIRCUIT 有权
标题翻译：补偿阻抗校准电路
公开(公告)号：US20140184267A1
公开(公告)日：2014-07-03
申请号：US13732713
申请日：2013-01-02
申请人： Brian D. Jones , Jeffrey H. Sloan , Xiaopeng Wang
发明人： Brian D. Jones , Jeffrey H. Sloan , Xiaopeng Wang
IPC分类号： H03K19/0175 , G06F17/50
CPC分类号： H03K19/0005 , H03K19/00361 , H03K19/017545
摘要： Aspects of the invention provide for compensating impedance calibration circuits. In one embodiment, a compensated impedance calibration circuit, includes: a variable resistor network including a tunable resistor and a fixed resistor; and an external resistance network including a target external precision resistor and a parasitic distribution resistance; wherein a resistance of the variable resistor network is proportional to a resistance of the external resistance network, such that a ratio of an output voltage of the variable resistor network to a power supply voltage is constant.
摘要翻译：本发明的方面提供补偿阻抗校准电路。在一个实施例中，补偿阻抗校准电路包括：包括可调电阻器和固定电阻器的可变电阻器网络; 以及包括目标外部精密电阻器和寄生配电电阻的外部电阻网络; 其中所述可变电阻器网络的电阻与所述外部电阻网络的电阻成比例，使得所述可变电阻器网络的输出电压与电源电压的比率是恒定的。

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