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1. 发明授权

US06603812B1 Hardware implementation of a decimating finite impulse response filter 有权
标题翻译：抽取有限脉冲响应滤波器的硬件实现
公开(公告)号：US06603812B1
公开(公告)日：2003-08-05
申请号：US09135229
申请日：1998-08-17
申请人： Florin A. Oprescu
发明人： Florin A. Oprescu
IPC分类号： H03H730
CPC分类号： H03H17/0664 , H03H2218/10
摘要： The invention provides apparatus and methods for generating the coefficients of a finite impulse response digital filter used in signal sample rate conversion. Sequence generation circuitry provides a discrete-time sequence x(n) that is coupled to a plurality of cascaded discrete-time integrators that generate the filter coefficients h(n). Bit serial and interleaved bit serial implementations are described that provide efficient coefficient generators. The described apparatus and methods also may be used to efficiently implement a finite impulse response digital filter for an oversampling analog-to-digital converter.
摘要翻译：本发明提供用于产生信号采样率转换中使用的有限脉冲响应数字滤波器的系数的装置和方法。序列生成电路提供耦合到产生滤波器系数h（n）的多个级联离散时间积分器的离散时间序列x（n）。描述了提供有效系数发生器的位串行和交错位串行实现。所描述的装置和方法也可用于有效地实现用于过采样模数转换器的有限脉冲响应数字滤波器。

2. 发明授权

US08330633B2 Current steering circuit with feedback 有权
标题翻译：电流转向电路带反馈
公开(公告)号：US08330633B2
公开(公告)日：2012-12-11
申请号：US13096737
申请日：2011-04-28
申请人： James L. Brubaker , Florin A. Oprescu
发明人： James L. Brubaker , Florin A. Oprescu
IPC分类号： H03M1/66
CPC分类号： H03M1/0614 , H03K17/007 , H03K17/162 , H03K17/693 , H03M1/742
摘要： A differential current steering (CS) circuit uses feedback from the differential output nodes A and B to cause current steering devices (e.g., MOSFETs) to effectively exhibit an infinite output impedance when conducting. Therefore, the signal on the output nodes A or B does not significantly change the voltage at the common node, This is particularly useful when the differential output nodes are connected to differential output buses in a digital-to-analog converter. The circuit dynamically cancels, though feedback, the signal induced at the common node by the signal present at the “steered” output node. Therefore, the CS circuit effectively presents an infinite output impedance between the common node and the output nodes. In some cases, it may be desirable to not create a substantially infinite output impedance for the CS circuit but control the impedance to a predefined level to counter other distortions in the system.
摘要翻译：差分电流转向（CS）电路使用来自差分输出节点A和B的反馈，以使电流转向装置（例如，MOSFET）在导通时有效地呈现无限的输出阻抗。因此，输出节点A或B上的信号不会显着改变公共节点处的电压。当差分输出节点连接到数模转换器中的差分输出总线时，这尤其有用。该电路通过反馈来动态地消除在转向输出节点处存在的信号在公共节点处感应的信号。因此，CS电路有效地在公共节点和输出节点之间呈现无限大的输出阻抗。在某些情况下，可能不希望为CS电路产生基本上无限的输出阻抗，但是将阻抗控制到预定义的水平以抵消系统中的其它失真。

3. 发明授权

US06208279B1 Single-cycle oversampling analog-to-digital converter 有权
标题翻译：单周期过采样模数转换器
公开(公告)号：US06208279B1
公开(公告)日：2001-03-27
申请号：US09135159
申请日：1998-08-17
申请人： Florin A. Oprescu
发明人： Florin A. Oprescu
IPC分类号： H03M300
CPC分类号： H03M3/374 , H03M3/43 , H03M3/452 , H03M3/462
摘要： An oversampling delta-sigma analog-to-digital converter suitable for single-cycle operation is provide. In a preferred embodiment of the present invention, only one multiply-accumulate processor is present in the digital filtering stage for decimating the output sequence R(I). A system controller produces precisely timed modulator enable (EnM) and digital filter enable (EnF) signals for coordinating activation of certain circuit elements and for managing power consumption of the system.
摘要翻译：提供了适用于单周期操作的过采样delta-sigma模数转换器。在本发明的优选实施例中，在数字滤波级中仅存在一个乘法累加处理器，用于抽取输出序列R（I）。系统控制器产生精确定时的调制器使能（EnM）和数字滤波器使能（EnF）信号，用于协调某些电路元件的激活和管理系统的功耗。

4. 发明授权

US5592510A Common mode early voltage compensation subcircuit for current driver 失效
标题翻译：共模早期电压补偿电流为当前驱动器
公开(公告)号：US5592510A
公开(公告)日：1997-01-07
申请号：US219664
申请日：1994-03-29
申请人： Roger W. Van Brunt , Florin A. Oprescu
发明人： Roger W. Van Brunt , Florin A. Oprescu
IPC分类号： H03F3/45 , H04L5/20 , H04L25/02 , H04B1/38 , H04L5/16
CPC分类号： H04L25/0282 , H03F3/45179 , H03F3/45475 , H03F3/45654 , H03F3/45766 , H04L25/0274 , H04L5/20 , H03F2203/45394 , H03F2203/45592 , H04L25/029
摘要： In a driver circuit for a twisted pair cable, a compensator for preventing appreciable common mode current flow into or out of the twisted pair cable in response to the device receiving a wide range of common mode voltage bias levels. A wide range of external bias voltages may be received as a result of variations in the ground node voltages of two coupled devices. The compensator circuit utilizes a feed back loop and monitors the bias voltage received on the twisted pair cable. As the magnitude of the common mode current increases due to external bias voltage variation from a reference bias voltage, the current flow of p-channel transistors, coupled in an arrangement of the present invention, is increased (or decreased, as necessary) so that reduced common mode current flows onto the twisted pair cable. The present invention reduces appreciable common mode current flow through the twisted pair cable from the driver that are due to variations in the external bias voltage between communication devices. The present invention provides high common mode output impedance for the driver circuit by altering the effective common mode common mode early voltage characteristics of the driver circuit while utilizing shorter channel length transistors for high speed communication capacity. The present invention also offers reduced current supply capacity of the common mode bias voltage source. The present invention operates ideally within driver circuits compatible with the IEEE P1394 communication standard.
摘要翻译：在用于双绞线电缆的驱动器电路中，响应于接收宽范围的共模电压偏置电平的装置，用于防止明显的共模电流流入或流出双绞线电缆的补偿器。作为两个耦合器件的接地节点电压变化的结果，可以接收大范围的外部偏置电压。补偿电路利用反馈回路来监测双绞线上接收的偏置电压。当共模电流的大小由于从参考偏置电压的外部偏置电压变化而增加时，在本发明的配置中耦合的p沟道晶体管的电流增加（或根据需要减少），使得降低的共模电流流向双绞线电缆。本发明通过来自驱动器的双绞线电缆减少由于通信设备之间的外部偏置电压的变化而引起的明显的共模电流。本发明通过改变驱动电路的有效共模共模早期电压特性，同时利用较短的沟道长度晶体管实现高速通信容量，为驱动电路提供高共模输出阻抗。本发明还提供了共模偏置电压源的降低的电流供应能力。本发明理想地在符合IEEE P1394通信标准的驱动器电路内运行。

5. 发明申请

US20080007442A1 Range compression in oversampling analog-to-digital converters using differential input signals 有权
公开(公告)号：US20080007442A1
公开(公告)日：2008-01-10
申请号：US11483390
申请日：2006-07-07
申请人： Florin A. Oprescu
发明人： Florin A. Oprescu
IPC分类号： H03M1/12
CPC分类号： H03M3/49 , H03M3/43 , H03M3/456
摘要： An analog-to-digital converter according to the invention is provided. The analog-to-digital converter preferably includes an analog input signal, a first reference signal, a second reference signal, and a range compression signal. The range compression signal is preferably characterized by a magnitude greater than the first reference signal and smaller than the second reference signal. In addition, when the analog input signal is sampled N times and the range compression signal is sampled N1 times, a compression factor related at least in part to the ratio N1/(N+N1) is obtained.

6. 发明申请

US20080007435A1 Range compression in oversampling analog-to-digital converters 有权
公开(公告)号：US20080007435A1
公开(公告)日：2008-01-10
申请号：US11483420
申请日：2006-07-07
申请人： Florin A. Oprescu
发明人： Florin A. Oprescu
IPC分类号： H03M7/00
CPC分类号： H03M3/49 , H03M3/43 , H03M3/456
摘要： An analog-to-digital converter according to the invention is provided. The analog-to-digital converter preferably includes an analog input signal, a first reference signal, a second reference signal, and a range compression signal. The range compression signal is preferably characterized by a magnitude greater than the first reference signal and smaller than the second reference signal. In addition, when the analog input signal is sampled N times and the range compression signal is sampled N1 times, a compression factor that is based at least in part on N1/(N+N1) is obtained.

7. 发明授权

US5485488A Circuit and method for twisted pair current source driver 失效
标题翻译：双绞线电流源驱动电路及方法
公开(公告)号：US5485488A
公开(公告)日：1996-01-16
申请号：US219728
申请日：1994-03-29
申请人： Roger W. Van Brunt , Florin A. Oprescu
发明人： Roger W. Van Brunt , Florin A. Oprescu
IPC分类号： H04L5/20 , H04L25/02 , H04B3/00
CPC分类号： H04L25/028 , H04L25/0276 , H04L5/20
摘要： A mechanism and method for efficiently communicating information regarding particular communication rate ("speed signal") between two or more communication stations (of a communication network). The transmitter operates on the IEEE P1394 High Performance Serial Bus to supply both differential and common mode signaling required by the IEEE standard for exemplary data transfer rates of 100 and 200 Mbit transmission. The present invention includes a transmission circuit that may operate in a differential signal mode and simultaneously in a common mode signal mode both utilizing a twisted pair cable. Data may be transmitted on the twisted pair at small differential signals. Information regarding the signal speed between two coupled units may be simultaneously transmitted using variations in the common mode voltage over the twisted pair. Communication may be initiated at a slower communication rate and then upgraded as appropriate for the two units. The present invention allows an efficient single circuit mechanism for communication units to transmit differential data and also to signal the use of a high speed communication rate with a common mode voltage. The present invention is especially useful within networks having units of varying versions and signal transfer rates.
摘要翻译：一种用于有效地传送关于通信网络的两个或多个通信站之间的特定通信速率（“速度信号”）的信息的机制和方法。发射机在IEEE P1394高性能串行总线上工作，为100和200 Mbit传输的示例性数据传输速率提供IEEE标准要求的差分和共模信号。本发明包括一种传输电路，其可以在差分信号模式下工作，并且同时处于采用双绞线电缆的共模信号模式。数据可以通过小差分信号在双绞线上传输。可以使用双绞线上的共模电压的变化同时发送关于两个耦合单元之间的信号速度的信息。通信可以以较慢的通信速率发起，然后根据两个单元进行升级。本发明允许用于通信单元的有效单电路机构发送差分数据，并且还用信号通知使用具有共模电压的高速通信速率。本发明在具有不同版本和信号传送速率的单元的网络内特别有用。

8. 发明申请

US20120274496A1 Current Steering Circuit with Feedback 有权
标题翻译：当前转向回路与反馈
公开(公告)号：US20120274496A1
公开(公告)日：2012-11-01
申请号：US13096737
申请日：2011-04-28
申请人： James L. Brubaker , Florin A. Oprescu
发明人： James L. Brubaker , Florin A. Oprescu
IPC分类号： H03M1/66 , H03L5/00
CPC分类号： H03M1/0614 , H03K17/007 , H03K17/162 , H03K17/693 , H03M1/742
摘要： A differential current steering (CS) circuit uses feedback from the differential output nodes A and B to cause current steering devices (e.g., MOSFETs) to effectively exhibit an infinite output impedance when conducting. Therefore, the signal on the output nodes A or B does not significantly change the voltage at the common node, This is particularly useful when the differential output nodes are connected to differential output buses in a digital-to-analog converter. The circuit dynamically cancels, though feedback, the signal induced at the common node by the signal present at the “steered” output node. Therefore, the CS circuit effectively presents an infinite output impedance between the common node and the output nodes. In some cases, it may be desirable to not create a substantially infinite output impedance for the CS circuit but control the impedance to a predefined level to counter other distortions in the system.
摘要翻译：差分电流转向（CS）电路使用来自差分输出节点A和B的反馈，以使电流转向装置（例如，MOSFET）在导通时有效地呈现无限的输出阻抗。因此，输出节点A或B上的信号不会显着改变公共节点处的电压。当差分输出节点连接到数模转换器中的差分输出总线时，这尤其有用。该电路通过反馈来动态地消除在转向输出节点处存在的信号在公共节点处感应的信号。因此，CS电路有效地在公共节点和输出节点之间呈现无限大的输出阻抗。在某些情况下，可能不希望为CS电路产生基本上无限的输出阻抗，但是将阻抗控制到预定义的水平以抵消系统中的其它失真。

9. 发明授权

US07420491B2 Analog signal sampling system and method having reduced average input current 有权
标题翻译：模拟信号采样系统和方法具有降低的平均输入电流
公开(公告)号：US07420491B2
公开(公告)日：2008-09-02
申请号：US11477159
申请日：2006-06-27
申请人： Florin A. Oprescu
发明人： Florin A. Oprescu
IPC分类号： H03M1/00
CPC分类号： H03M3/322 , H03M3/43 , H03M3/456 , H03M3/496
摘要： A novel sampling system having a sampling device responsive to an analog input signal and a reference signal for providing corresponding charges. A switching circuit is provided to supply the input signal and the reference signal to the sampling device. The switching circuit is controlled to supply the input signal and the reference signal to the sampling device so as provide a substantially zero total charge taken by the sampling device from a source of the input signal. One application of the foregoing is in analog-to-digital conversion.
摘要翻译：一种新颖的采样系统，其具有响应于模拟输入信号的采样装置和用于提供相应电荷的参考信号。提供开关电路以将输入信号和参考信号提供给采样装置。控制开关电路以将输入信号和参考信号提供给采样装置，以便从输入信号的源提供由采样装置采取的基本上零的总电荷。上述的一个应用是在模数转换中。

10. 发明授权

US07397403B2 Range compression in oversampling analog-to-digital converters using differential input signals 有权
标题翻译：使用差分输入信号的过采样模数转换器中的范围压缩
公开(公告)号：US07397403B2
公开(公告)日：2008-07-08
申请号：US11483390
申请日：2006-07-07
申请人： Florin A. Oprescu
发明人： Florin A. Oprescu
IPC分类号： H03M1/00
CPC分类号： H03M3/49 , H03M3/43 , H03M3/456
摘要： An analog-to-digital converter according to the invention is provided. The analog-to-digital converter preferably includes an analog input signal, a first reference signal, a second reference signal, and a range compression signal. The range compression signal is preferably characterized by a magnitude greater than the first reference signal and smaller than the second reference signal. In addition, when the analog input signal is sampled N times and the range compression signal is sampled N1 times, a compression factor related at least in part to the ratio N1/(N+N1) is obtained.
摘要翻译：提供了根据本发明的模拟 - 数字转换器。模数转换器优选地包括模拟输入信号，第一参考信号，第二参考信号和范围压缩信号。范围压缩信号的特征在于大于第一参考信号并且小于第二参考信号的幅度。此外，当模拟输入信号被采样N次并且范围压缩信号被采样N1次时，获得至少部分地与比率N1 /（N + N1）相关的压缩因子。

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