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1. 发明授权

US06879316B2 Pointing device with pressure sensitive resistor 有权
标题翻译：带压敏电阻的指示装置
公开(公告)号：US06879316B2
公开(公告)日：2005-04-12
申请号：US10010072
申请日：2001-12-11
申请人： Florian Max Kehlstadt , Baptiste Merminod , Laurent Plancherel , Emmanuel Dubois
发明人： Florian Max Kehlstadt , Baptiste Merminod , Laurent Plancherel , Emmanuel Dubois
IPC分类号： G06F3/0354 , G06F3/0485 , G09G5/08 , G09G5/00
CPC分类号： G06F3/0485 , G06F3/03543
摘要： An input device with a pressure-sensitive element using a pressure sensing resistor. A solid elastomeric material is mounted over the pressure sensing resistor to transfer a force from the user's finger to the pressure sensitive resistor without visible deformation of the elastomeric material. This provides a comfortable button for a user which does not require the compression of a domed cap to provide pressure-sensing input. In another aspect of the invention, a pressure-sensing input element utilizes both the amount of pressure and the amount of time to determine the type of signal provided to the electronic system. In another aspect of the present invention, an input device contains a first scrolling element (e.g. a wheel) and includes a switch button mounted close to the scrolling element to activate continuous scrolling. In one embodiment of the invention, the pressure sensing resistor used is a folded-over metal-coated plastic film which is responsive to very low activation forces, such as forces less than 50 grams.
摘要翻译：具有使用压力感测电阻器的压敏元件的输入装置。将固体弹性体材料安装在压力感测电阻器上方以将来自用户的手指的力传递到压敏电阻器，而弹性体材料没有可见的变形。这为用户提供了舒适的按钮，其不需要压缩圆顶帽来提供压力感测输入。在本发明的另一方面，压力感测输入元件利用压力的量和时间量来确定提供给电子系统的信号的类型。在本发明的另一方面，一种输入装置包含第一滚动元件（例如轮子），并且包括靠近滚动元件安装的开关按钮，以激活连续滚动。在本发明的一个实施例中，使用的压力感测电阻器是折叠金属涂覆的塑料膜，其对非常低的激活力（例如小于50克的力）有反应。

2. 发明授权

US06774451B2 Mos transistor for high density integration circuits 有权
标题翻译： Mos晶体管用于高密度集成电路
公开(公告)号：US06774451B2
公开(公告)日：2004-08-10
申请号：US10204530
申请日：2003-01-06
申请人： Emmanuel Dubois
发明人： Emmanuel Dubois
IPC分类号： H01L27095
CPC分类号： H01L29/78654 , H01L29/7839
摘要： This invention relates to a MOS transistor made in the thin film of silicon of an SOI chip (10), said thin film (13) being slightly doped and of less than 30 nm in thickness, the source (14) and drain (15) contacts being of the Schottky type at the lowest level of Schottky barrier possible for majority carriers, with an accumulation type transistor operation.
摘要翻译：本发明涉及一种在SOI芯片（10）的硅薄膜中形成的MOS晶体管，所述薄膜（13）是稍微掺杂且厚度小于30nm，源极（14）和漏极（15）触点在肖特基势垒的最底层是肖特基型的，对于多数载流子是可能的，具有堆积型晶体管操作。

3. 发明授权

US08362570B2 Method for making complementary P and N MOSFET transistors, electronic device including such transistors, and processor including at least one such device 有权
标题翻译：制造互补P和N MOSFET晶体管的方法，包括这种晶体管的电子器件，以及包括至少一个这样的器件的处理器
公开(公告)号：US08362570B2
公开(公告)日：2013-01-29
申请号：US12937193
申请日：2009-04-09
申请人： Guilhem Larrieu , Emmanuel Dubois
发明人： Guilhem Larrieu , Emmanuel Dubois
IPC分类号： H01L21/02
CPC分类号： H01L29/665 , H01L21/2257 , H01L21/26513 , H01L21/7624 , H01L21/823814 , H01L21/84 , H01L27/1203 , H01L29/66643 , H01L29/7839
摘要： This method for making complementary p and n MOSFET transistors with Schottky source and drain electrodes controlled by a gate electrode, comprising: making source and drain electrodes from a single silicide for both p and n transistors; segregating first impurities from groups II and III of the periodic table at the interface between the silicide and the channel of the p transistor, the complementary n transistor being masked; and segregating second impurities from groups V and VI of the periodic table, at the interface between the silicide and the channel of the n transistor, and the complementary p transistor being masked.
摘要翻译：用于制造具有由栅电极控制的肖特基源极和漏电极的互补p和n MOSFET晶体管的方法，包括：从单个硅化物制造源极和漏极用于p和n晶体管; 在硅化物和p晶体管的沟道之间的界面处将元素周期表的第II和III族的第一杂质分离，互补n晶体管被掩蔽; 并且在硅化物和n型晶体管的沟道之间的界面处，并且互补的p晶体管被掩蔽，从而将元素周期表的V族和VI族的第二杂质分离出来。

4. 发明申请

US20050024346A1 Digital pen function control 审中-公开
标题翻译：数码笔功能控制
公开(公告)号：US20050024346A1
公开(公告)日：2005-02-03
申请号：US10631434
申请日：2003-07-30
申请人： Jean-Luc Dupraz , Florian Kehlstadt , Emmanuel Dubois , Fabrice Lauper
发明人： Jean-Luc Dupraz , Florian Kehlstadt , Emmanuel Dubois , Fabrice Lauper
IPC分类号： G06F3/033 , G09G5/00
CPC分类号： G06F3/03545
摘要： A digital writing system according to one embodiment of the present invention captures handwritten gestures in addition to text and patterns. It may include, among other things, a digital pen, special erasable ink and paper, and application software for the managing of captured files with a corresponding user interface. A digital pen according to one embodiment of the present invention may include character recognition subsystem, function control subsystem with selection mechanisms, a processor subsystem, memory subsystems, and wired or wireless communication subsystems. In addition, embodiments of a digital pen according to the present invention may include additional functional features including, for example, a user notification (e.g., alarm) feature, a digital camera feature, voice recording and recognition features, calendar features, calculator features, biometric sensor features, and the like.
摘要翻译：根据本发明的一个实施例的数字写入系统除了文本和图案之外还捕获手写手势。它可以包括数字笔，特殊的可擦除墨水和纸张以及用于使用相应的用户界面来管理所捕获的文件的应用软件。根据本发明的一个实施例的数字笔可以包括字符识别子系统，具有选择机制的功能控制子系统，处理器子系统，存储器子系统以及有线或无线通信子系统。此外，根据本发明的数字笔的实施例可以包括额外的功能特征，包括例如用户通知（例如，报警）特征，数字照相机特征，语音记录和识别特征，日历特征，计算器特征，生物特征传感器特征等。

5. 发明申请

US20110121400A1 METHOD FOR MAKING COMPLEMENTARY P AND N MOSFET TRANSISTORS, ELECTRONIC DEVICE INCLUDING SUCH TRANSISTORS, AND PROCESSOR INCLUDING AT LEAST ONE SUCH DEVICE 有权
标题翻译：用于制造补充P和N MOSFET晶体管的方法，包括这种晶体管的电子器件，以及包括至少一个这样的器件的处理器
公开(公告)号：US20110121400A1
公开(公告)日：2011-05-26
申请号：US12937193
申请日：2009-04-09
申请人： Guilhem Larrieu , Emmanuel Dubois
发明人： Guilhem Larrieu , Emmanuel Dubois
IPC分类号： H01L27/092 , H01L21/8238 , H01L21/786
CPC分类号： H01L29/665 , H01L21/2257 , H01L21/26513 , H01L21/7624 , H01L21/823814 , H01L21/84 , H01L27/1203 , H01L29/66643 , H01L29/7839
摘要： This method for making complementary p and n MOSFET transistors with Schottky source and drain electrodes controlled by a gate electrode, comprising: making source and drain electrodes from a single silicide for both p and n transistors; segregating first impurities from groups II and III of the periodic table at the interface between the silicide and the channel of the p transistor, the complementary n transistor being masked; and segregating second impurities from groups V and VI of the periodic table, at the interface between the silicide and the channel of the n transistor, and the complementary p transistor being masked.
摘要翻译：用于制造具有由栅电极控制的肖特基源极和漏电极的互补p和n MOSFET晶体管的方法，包括：从单个硅化物制造源极和漏极用于p和n晶体管; 在硅化物和p晶体管的沟道之间的界面处将元素周期表的第II和III族的第一杂质分离，互补n晶体管被掩蔽; 并且在硅化物和n型晶体管的沟道之间的界面处，并且互补的p晶体管被掩蔽，从而将元素周期表的V族和VI族的第二杂质分离出来。

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