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1. 发明授权

US06732136B1 Differential, low voltage swing reducer 失效
标题翻译：差动，低压摆动减速机
公开(公告)号：US06732136B1
公开(公告)日：2004-05-04
申请号：US09471201
申请日：1999-12-23
申请人： Feng Chen , Thomas Fletcher , Shahram Jamshidi
发明人： Feng Chen , Thomas Fletcher , Shahram Jamshidi
IPC分类号： G06F750
CPC分类号： G06F7/607
摘要： A small swing reducer circuit. An apparatus includes a first number of input terminals including at least two input terminals coupled to receive a differential small swing signal and a reducer circuit to generate differential, small swing sum and carry output signals based on data received via the input terminals.
摘要翻译：小摆动减速电路。一种装置包括：第一数量的输入端子，包括耦合以接收差分小摆动信号的至少两个输入端子;以及还原电路，用于根据经由输入端子接收到的数据产生微分，小摆幅和输入输出信号。

2. 发明授权

US5646558A Plurality of distinct multiplexers that operate as a single multiplexer 失效
标题翻译：作为单个多路复用器工作的多种不同的多路复用器
公开(公告)号：US5646558A
公开(公告)日：1997-07-08
申请号：US534598
申请日：1995-09-27
申请人： Shahram Jamshidi
发明人： Shahram Jamshidi
IPC分类号： H03K17/00 , H03K17/693 , H03K19/084 , H03K19/094
CPC分类号： H03K17/693 , H03K17/005
摘要： A multiplexing arrangement. The multiplexing arrangement comprises a set of data inputs wherein a first multiplexer is coupled to a first subset of the set of data inputs and a second multiplexer is coupled to a second subset of the set of data inputs. Only one of the first and second multiplexers is selected to pass one of the set of data inputs at any given time. A logic gate is coupled to the first and second data outputs, and the logic gate synthesizes an output signal for the multiplexing arrangement in response to values output by the first and second multiplexers such that the multiplexing arrangement operates as a single multiplexer. According to one embodiment, the multiplexer that is not selected to pass data has its output biased to a known state.
摘要翻译：复用布置。多路复用布置包括一组数据输入，其中第一多路复用器耦合到该组数据输入的第一子集，第二多路复用器耦合到该组数据输入的第二子集。选择第一和第二多路复用器中的一个在任何给定时间通过该组数据输入中的一个。逻辑门耦合到第一和第二数据输出，并且逻辑门响应于由第一和第二多路复用器输出的值合成用于复用装置的输出信号，使得多路复用布置作为单个复用器工作。根据一个实施例，未选择传递数据的多路复用器的输出偏置到已知状态。

3. 发明授权

US5625303A Multiplexer having a plurality of internal data paths that operate at different speeds 失效
标题翻译：多路复用器具有以不同速度操作的多个内部数据路径
公开(公告)号：US5625303A
公开(公告)日：1997-04-29
申请号：US534485
申请日：1995-09-27
申请人： Shahram Jamshidi
发明人： Shahram Jamshidi
IPC分类号： H03K17/693 , H03K19/084 , H03K19/094
CPC分类号： H03K17/693
摘要： A multiplexer. The multiplexer comprises a first data input and a second data input coupled to a logic gate via a first data path and a second data path, respectively, wherein a maximum of one of the first and second data paths is enabled to pass data at any given time. The data paths are independent of one another such that devices of the first data path do not load the second data path, and vice versa. The speed of a data path is determined by how many data input signals are routed through the same data path. In this manner, the speed of each data path may be tuned as required to provide the necessary operating speeds.
摘要翻译：多路复用器多路复用器包括分别经由第一数据路径和第二数据路径耦合到逻辑门的第一数据输入和第二数据输入，其中第一和第二数据路径中的最多一个能够在任何给定的时间。数据路径彼此独立，使得第一数据路径的设备不加载第二数据路径，反之亦然。数据路径的速度由通过相同数据路径路由多少数据输入信号确定。以这种方式，可以根据需要调整每个数据路径的速度以提供必要的操作速度。

4. 发明授权

US5598114A High speed reduced area multiplexer 失效
标题翻译：高速缩小区域复用器
公开(公告)号：US5598114A
公开(公告)日：1997-01-28
申请号：US534487
申请日：1995-09-27
申请人： Shahram Jamshidi
发明人： Shahram Jamshidi
IPC分类号： H03K17/00 , H03K17/693 , H03K19/094 , H03K19/084
CPC分类号： H03K17/693 , H03K17/005
摘要： A multiplexer that comprises a first input buffer and a first pass gate coupled in series between a first data input and a common node and a second input buffer and a second pass gate coupled in series between a second data input and the common node. A biasing circuit is coupled to the common node and a supply voltage to bias the common node to the supply voltage when neither pass gate is switched on to pass data from its corresponding input buffer to the common node. An output buffer is coupled to the common node for outputting an output signal to a data output in response to a voltage of the common node.
摘要翻译：一种多路复用器，包括串联耦合在第一数据输入和公共节点之间的第一输入缓冲器和第一通过栅极，以及串联耦合在第二数据输入和公共节点之间的第二输入缓冲器和第二通过栅极。一个偏置电路耦合到公共节点和一个电源电压，以在两个通过门被接通时将公共节点偏置到电源电压，以将数据从其对应的输入缓冲器传递到公共节点。输出缓冲器耦合到公共节点，用于响应于公共节点的电压将输出信号输出到数据输出。

5. 发明授权

US07592840B2 Domino circuit with disable feature 失效
标题翻译：具有禁用功能的Domino电路
公开(公告)号：US07592840B2
公开(公告)日：2009-09-22
申请号：US11557913
申请日：2006-11-08
申请人： Kin Yip Sit , Shahram Jamshidi
发明人： Kin Yip Sit , Shahram Jamshidi
IPC分类号： H03K19/00
CPC分类号： H03K19/094
摘要： Some embodiments provide dynamic circuits with dynamic nodes that may float during a disable mode to reduce leakage.
摘要翻译：一些实施例提供具有在禁用模式期间浮动以减少泄漏的动态节点的动态电路。

6. 发明申请

US20080106302A1 DOMINO CIRCUIT WITH DISABLE FEATURE 失效
标题翻译：多米尼克电路具有禁用功能
公开(公告)号：US20080106302A1
公开(公告)日：2008-05-08
申请号：US11557913
申请日：2006-11-08
申请人： Kin Yip Sit , Shahram Jamshidi
发明人： Kin Yip Sit , Shahram Jamshidi
IPC分类号： H03K19/094
CPC分类号： H03K19/094
摘要： Some embodiments provide dynamic circuits with dynamic nodes that may float during a disable mode to reduce leakage.
摘要翻译：一些实施例提供具有在禁用模式期间浮动以减少泄漏的动态节点的动态电路。

7. 发明授权

US06707318B2 Low power entry latch to interface static logic with dynamic logic 失效
标题翻译：低功率输入锁存器，用于将静态逻辑与动态逻辑相连接
公开(公告)号：US06707318B2
公开(公告)日：2004-03-16
申请号：US10107740
申请日：2002-03-26
申请人： Sudarshan Kumar , Shahram Jamshidi
发明人： Sudarshan Kumar , Shahram Jamshidi
IPC分类号： H03K19096
CPC分类号： H03K3/356173 , H03K3/012 , H03K19/0963
摘要： An entry latch to provide a dynamic signal at an output port in response to input static signals at a pulldown network, the pulldown network to conditionally discharge an internal node depending upon the input static signals, the entry latch comprising a pass transistor having a first source/drain connected to the output port and a second source/drain connected to a gate of a pullup pMOSFET, where the pullup pMOSFET turns ON only if the pulldown network does not turn ON during the evaluation phase.
摘要翻译：输入锁存器，用于响应于下拉网络处的输入静态信号在输出端口处提供动态信号，所述下拉网络根据输入的静态信号来有条件地排放内部节点，所述输入锁存器包括具有第一源的传输晶体管 /漏极连接到输出端口，第二个源极/漏极连接到上拉pMOSFET的栅极，其中只有在评估阶段下拉网络未导通时，上拉电阻pOSOSFET才会导通。

8. 发明授权

US07302652B2 Leakage control in integrated circuits 有权
标题翻译：集成电路中的泄漏控制
公开(公告)号：US07302652B2
公开(公告)日：2007-11-27
申请号：US10404937
申请日：2003-03-31
申请人： Zhanping Chen , Lakshman Thiruvenkatachari , Shahram Jamshidi
发明人： Zhanping Chen , Lakshman Thiruvenkatachari , Shahram Jamshidi
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F2217/08
摘要： Although there are a number of techniques available to reduce leakage current, there is still considerable room for improvement. Accordingly, the present inventors devised, among other things, an exemplary method which entails defining first and second leakage-reduction vectors for respective first and second portions of an integrated circuit, such as a microprocessor. The leakage-reduction vectors, in some embodiments, set the first and second portion to minimum leakage states and thus promise to reduce leakage power and extend battery life in devices that incorporate this technology.
摘要翻译：虽然有许多技术可以减少泄漏电流，但仍有相当大的改进空间。因此，本发明人设计了一种示例性方法，其需要为诸如微处理器的集成电路的各个第一和第二部分定义第一和第二泄漏减少向量。在一些实施例中，泄漏减少矢量将第一部分和第二部分设置为最小的泄漏状态，并且因此有助于降低泄漏功率并延长结合该技术的设备中的电池寿命。

9. 发明授权

US06952118B2 Gate-clocked domino circuits with reduced leakage current 失效
标题翻译：具有降低漏电流的门控多米诺骨牌电路
公开(公告)号：US06952118B2
公开(公告)日：2005-10-04
申请号：US10324307
申请日：2002-12-18
申请人： Shahram Jamshidi , Sudarshan Kumar
发明人： Shahram Jamshidi , Sudarshan Kumar
IPC分类号： H03K19/096
CPC分类号： H03K19/0963
摘要： A gate-clocked domino circuit with reduced leakage current during an inactive state, where domino stages in the domino circuit have long channel length transistors in the pre-charge paths. During an inactive state, the domino stages are put in an evaluation state and are discharged.
摘要翻译：在非活动状态下具有减小的漏电流的门时多米诺骨牌电路，其中多米诺骨牌电路中的多米诺级在预充电路径中具有长通道长度的晶体管。在非活动状态期间，多米诺骨牌阶段被置于评估状态并被排除。

10. 发明授权

US06914848B2 Word line transistor stacking for leakage control 失效
标题翻译：字线晶体管堆叠用于泄漏控制
公开(公告)号：US06914848B2
公开(公告)日：2005-07-05
申请号：US10461562
申请日：2003-06-12
申请人： Shahram Jamshidi , Sadarshan Kumar , Sadhana Madhyastha
发明人： Shahram Jamshidi , Sadarshan Kumar , Sadhana Madhyastha
IPC分类号： G11C8/00 , G11C8/08
CPC分类号： G11C8/08
摘要： A memory, such as a register file or a cache, having stack pMOSFETs shared among its word line drivers, where a stack pMOSFET shared by a set of word line drivers has its drain connected to the sources of the pMOSFETs in the set or word line drivers, and were each stack pMOSFET is controlled by an enable signal so as to turn ON only if its corresponding set of word line drivers is enabled. The enable signal may be provided by a write or read enable port, or by the memory's address decoder. The stacked configuration of pMOSFETs significantly reduces sub-threshold leakage current in the word line drivers with very little penalty in performance.
摘要翻译：诸如寄存器文件或高速缓存的存储器在其字线驱动器之间共享堆栈pMOSFET，其中由一组字线驱动器共享的堆栈pMOSFET的漏极连接到集合或字线中的pMOSFET的源极驱动器，并且每个堆栈pMOSFET由使能信号控制，以便仅当其对应的字线驱动器组被使能时才导通。使能信号可以由写入或读取使能端口或由存储器的地址解码器提供。 pMOSFET的堆叠配置显着降低了字线驱动器中的次阈值泄漏电流，性能损失非常小。

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