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1. 发明申请

US20080028150A1 Autonomic Mode Switching for L2 Cache Speculative Accesses Based on L1 Cache Hit Rate 审中-公开
标题翻译：基于L1缓存命中率的L2缓存投机访问的自主模式切换
公开(公告)号：US20080028150A1
公开(公告)日：2008-01-31
申请号：US11460806
申请日：2006-07-28
申请人： Farnaz Toussi
发明人： Farnaz Toussi
IPC分类号： G06F12/00
CPC分类号： G06F12/0897 , G06F12/0862
摘要： A speculative access mechanism in a memory subsystem monitors hit rate of an L1 cache, and autonomically switches modes of speculative accesses to an L2 cache accordingly. If the L1 hit rate is less than a threshold, such as 50%, the speculative load mode for the L2 cache is set to load-cancel. If the L1 hit rate is greater than or equal to the threshold, the speculative load mode for the L2 cache is set to load-confirm. By autonomically adjusting the mode of speculative accesses to an L2 cache as the L1 hit rate changes, the performance of a computer system that uses speculative accesses to an L2 cache improves.
摘要翻译：存储器子系统中的推测访问机制监视L 1高速缓存的命中率，并且相应地自动地切换对L 2高速缓存的推测访问模式。如果L 1命中率小于50％的阈值，则将L 2高速缓存的推测负载模式设置为加载取消。如果L 1命中率大于或等于阈值，则将L 2高速缓存的推测加载模式设置为加载确认。随着L 1命中率的变化，通过自主地调整对L 2缓存的推测访问模式，使用对L 2高速缓存的推测访问的计算机系统的性能提高。

2. 发明授权

US08037252B2 Method for reducing coherence enforcement by selective directory update on replacement of unmodified cache blocks in a directory-based coherent multiprocessor 有权
标题翻译：用于通过选择性目录更新来减少基于目录的相干多处理器中未修改的高速缓存块的一致性执行的方法
公开(公告)号：US08037252B2
公开(公告)日：2011-10-11
申请号：US11845812
申请日：2007-08-28
申请人： Farnaz Toussi
发明人： Farnaz Toussi
IPC分类号： G06F12/00
CPC分类号： G06F12/0817
摘要： Embodiments of the present invention generally provide techniques and apparatus to reduce the number of memory directory updates during block replacement in a system having a directory-based cache. The system may be implemented to utilize a read/write bit to determine the accessibility of a cache line and limit memory directory updates during block replacement to regions that are determined to be readable and writable by multiple processors.
摘要翻译：本发明的实施例通常提供了在具有基于目录的高速缓存的系统中减少在块替换期间的存储器目录更新的数量的技术和装置。可以实现该系统以利用读/写位来确定高速缓存行的可访问性，并且在块替换期间将存储器目录更新限制为被多个处理器确定为可读写的区域。

3. 发明申请

US20080147977A1 DESIGN STRUCTURE FOR AUTONOMIC MODE SWITCHING FOR L2 CACHE SPECULATIVE ACCESSES BASED ON L1 CACHE HIT RATE 审中-公开
标题翻译：基于L1高速缓存速率的L2高速缓存接入的自动模式切换设计结构
公开(公告)号：US20080147977A1
公开(公告)日：2008-06-19
申请号：US12037378
申请日：2008-02-26
申请人： Farnaz Toussi
发明人： Farnaz Toussi
IPC分类号： G06F12/00
CPC分类号： G06F12/0862 , G06F11/3452 , G06F12/0897 , G06F2201/88 , G06F2201/885 , G06F2212/1016 , G06F2212/502
摘要： A design structure of a speculative access mechanism in a memory subsystem monitors hit rate of an L1 cache, and autonomically switches modes of speculative accesses to an L2 cache accordingly. If the L1 hit rate is less than a threshold, such as 50%, the speculative load mode for the L2 cache is set to load-cancel. If the L1 hit rate is greater than or equal to the threshold, the speculative load mode for the L2 cache is set to load-confirm. By autonomically adjusting the mode of speculative accesses to an L2 cache as the L1 hit rate changes, the performance of a computer system that uses speculative accesses to an L2 cache improves.
摘要翻译：存储器子系统中的推测访问机制的设计结构监视L1高速缓存的命中率，并相应地自主地切换对L2缓存的推测访问模式。如果L1命中率小于阈值（例如50％），则将L2高速缓存的推测负载模式设置为加载取消。如果L1命中率大于或等于阈值，则将L2高速缓存的推测加载模式设置为加载确认。通过自动调整L1命中率改变对L2缓存的推测访问模式，可以提高使用对L2缓存的推测性访问的计算机系统的性能。

4. 发明授权

US06874067B2 Eliminating unnecessary data pre-fetches in a multiprocessor computer system 失效
标题翻译：在多处理器计算机系统中消除不必要的数据预取
公开(公告)号：US06874067B2
公开(公告)日：2005-03-29
申请号：US10120991
申请日：2002-04-11
申请人： Farnaz Toussi
发明人： Farnaz Toussi
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0862 , G06F12/0831
摘要： A multiprocessor computer system employs a number of levels of cache memories with each processor. A cache controller for a lower level cache memory receives a memory block pre-fetch request which requests a particular memory block. The cache controller determines a likelihood that the particular memory block will be invalidated prior to use of the memory block by a processor which issued the pre-fetch request. Based on that determination, the cache controller determines whether to honor the pre-fetch request.
摘要翻译：多处理器计算机系统与每个处理器一起使用多个级别的高速缓冲存储器。用于低级缓存存储器的高速缓存控制器接收请求特定存储器块的存储器块预取请求。高速缓存控制器确定在由发出预取请求的处理器使用存储器块之前特定存储器块将被无效的可能性。基于该确定，缓存控制器确定是否遵守预取请求。

5. 发明授权

US07945739B2 Structure for reducing coherence enforcement by selective directory update on replacement of unmodified cache blocks in a directory-based coherent multiprocessor 有权
标题翻译：用于通过选择性目录更新来减少在基于目录的相干多处理器中未修改的高速缓存块的替换的结构
公开(公告)号：US07945739B2
公开(公告)日：2011-05-17
申请号：US12046293
申请日：2008-03-11
申请人： Farnaz Toussi
发明人： Farnaz Toussi
IPC分类号： G06F12/00
CPC分类号： G06F12/0817
摘要： A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design to reduce the number of memory directory updates during block replacement in a system having a directory-based cache is provided. The design structure may be implemented to utilize a read/write bit to determine the accessibility of a cache line and limit memory directory updates during block replacement to regions that are determined to be readable and writable by multiple processors.
摘要翻译：提供了一种体现在机器可读存储介质中的设计结构，用于在具有基于目录的高速缓存的系统中用于设计，制造和/或测试设计以减少在块替换期间的存储器目录更新的数量。可以实现设计结构以利用读/写位来确定高速缓存行的可访问性，并且在块替换期间将存储器目录更新限制为被多个处理器确定为可读写的区域。

6. 发明申请

US20090063782A1 Method for Reducing Coherence Enforcement by Selective Directory Update on Replacement of Unmodified Cache Blocks in a Directory-Based Coherent Multiprocessor 有权
标题翻译：通过选择性目录更新降低基于目录的相干多处理器中未修改的缓存块的一致性执行的方法
公开(公告)号：US20090063782A1
公开(公告)日：2009-03-05
申请号：US11845812
申请日：2007-08-28
申请人： Farnaz Toussi
发明人： Farnaz Toussi
IPC分类号： G06F12/00
CPC分类号： G06F12/0817
摘要： Embodiments of the present invention generally provide techniques and apparatus to reduce the number of memory directory updates during block replacement in a system having a directory-based cache. The system may be implemented to utilize a read/write bit to determine the accessibility of a cache line and limit memory directory updates during block replacement to regions that are determined to be readable and writable by multiple processors.
摘要翻译：本发明的实施例通常提供了在具有基于目录的高速缓存的系统中减少在块替换期间的存储器目录更新的数量的技术和装置。可以实现该系统以利用读/写位来确定高速缓存行的可访问性，并且在块替换期间将存储器目录更新限制为被多个处理器确定为可读写的区域。

7. 发明申请

US20090063771A1 STRUCTURE FOR REDUCING COHERENCE ENFORCEMENT BY SELECTIVE DIRECTORY UPDATE ON REPLACEMENT OF UNMODIFIED CACHE BLOCKS IN A DIRECTORY-BASED COHERENT MULTIPROCESSOR 有权
标题翻译：通过选择性目录更新在基于目录的相关多用户中更换未修改的高速缓存块的结构来减少协调执行的结构
公开(公告)号：US20090063771A1
公开(公告)日：2009-03-05
申请号：US12046293
申请日：2008-03-11
申请人： Farnaz Toussi
发明人： Farnaz Toussi
IPC分类号： G06F12/00
CPC分类号： G06F12/0817
摘要： A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design to reduce the number of memory directory updates during block replacement in a system having a directory-based cache is provided. The design structure may be implemented to utilize a read/write bit to determine the accessibility of a cache line and limit memory directory updates during block replacement to regions that are determined to be readable and writable by multiple processors.
摘要翻译：提供了一种体现在机器可读存储介质中的设计结构，用于在具有基于目录的高速缓存的系统中用于设计，制造和/或测试设计以减少在块替换期间的存储器目录更新的数量。可以实现设计结构以利用读/写位来确定高速缓存行的可访问性，并且在块替换期间将存储器目录更新限制为被多个处理器确定为可读写的区域。

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