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1. 发明授权

US08565030B2 Read boost circuit for memory device 有权
标题翻译：读取存储器件的升压电路
公开(公告)号：US08565030B2
公开(公告)日：2013-10-22
申请号：US13240861
申请日：2011-09-22
申请人： Fady Abouzeid , Sylvain Clerc , Philippe Roche
发明人： Fady Abouzeid , Sylvain Clerc , Philippe Roche
IPC分类号： G11C7/00
CPC分类号： G11C7/12 , G11C7/065 , G11C11/413
摘要： A read boost circuit arranged to boost the voltage difference between a pair of complementary bit lines of a memory device during a read operation, the read boost circuit including: a first transistor adapted to be controlled by the voltage level on a first bit line of the pair of bit lines to couple a second bit line of the pair of bit lines to a first supply voltage; and a second transistor connected directly to ground and adapted to be controlled by the voltage level on the second bit line to couple the first bit line to ground.
摘要翻译：一种读取升压电路，被布置为在读取操作期间升高存储器件的一对互补位线之间的电压差，读取升压电路包括：第一晶体管，其适于由第一晶体管的第一位线一对位线将一对位线的第二位线耦合到第一电源电压; 以及第二晶体管，其直接连接到地，并且适于由第二位线上的电压电平控制，以将第一位线耦合到地。

2. 发明申请

US20120081978A1 READ BOOST CIRCUIT FOR MEMORY DEVICE 有权
标题翻译：读取存储器件的升压电路
公开(公告)号：US20120081978A1
公开(公告)日：2012-04-05
申请号：US13240861
申请日：2011-09-22
申请人： Fady Abouzeid , Sylvain Clerc , Philippe Roche
发明人： Fady Abouzeid , Sylvain Clerc , Philippe Roche
IPC分类号： G11C7/00
CPC分类号： G11C7/12 , G11C7/065 , G11C11/413
摘要： A read boost circuit arranged to boost the voltage difference between a pair of complementary bit lines of a memory device during a read operation, the read boost circuit including: a first transistor adapted to be controlled by the voltage level on a first bit line of the pair of bit lines to couple a second bit line of the pair of bit lines to a first supply voltage; and a second transistor connected directly to ground and adapted to be controlled by the voltage level on the second bit line to couple the first bit line to ground.
摘要翻译：一种读取升压电路，被布置为在读取操作期间升高存储器件的一对互补位线之间的电压差，读取升压电路包括：第一晶体管，其适于由第一晶体管的第一位线一对位线将一对位线的第二位线耦合到第一电源电压; 以及第二晶体管，其直接连接到地，并且适于由第二位线上的电压电平控制，以将第一位线耦合到地。

3. 发明申请

US20120042292A1 METHOD OF SYNTHESIS OF AN ELECTRONIC CIRCUIT 审中-公开
标题翻译：电子电路合成方法
公开(公告)号：US20120042292A1
公开(公告)日：2012-02-16
申请号：US12853627
申请日：2010-08-10
申请人： Fady Abouzeid , Sylvain Clerc , Fabian Firmin
发明人： Fady Abouzeid , Sylvain Clerc , Fabian Firmin
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： A method of synthesis of at least one logic device coupled between first and second supply voltages and having a plurality of inputs and an output, the logic device including a plurality of transistors having a standard gate length, the method including: identifying, in the at least one logic device, one or more transistors connected between the first or second supply voltage and the output node; and increasing the gate length of each of the identified one or more transistors.
摘要翻译：一种合成耦合在第一和第二电源电压之间并具有多个输入和输出的至少一个逻辑器件的方法，所述逻辑器件包括具有标准栅极长度的多个晶体管，所述方法包括：在at 至少一个逻辑器件，连接在第一或第二电源电压与输出节点之间的一个或多个晶体管; 以及增加所识别的一个或多个晶体管中的每一个的栅极长度。

4. 发明授权

US08339172B2 Flip-flop with single clock phase and with reduced dynamic power 有权
标题翻译：触发器具有单时钟相位并具有降低的动态功耗
公开(公告)号：US08339172B2
公开(公告)日：2012-12-25
申请号：US12900147
申请日：2010-10-07
申请人： Fabian Firmin , Sylvain Clerc , Jean-Pierre Schoellkopf , Fady Abouzeid
发明人： Fabian Firmin , Sylvain Clerc , Jean-Pierre Schoellkopf , Fady Abouzeid
IPC分类号： H03K3/289
CPC分类号： H03K3/0372 , H03K3/356156 , H03K3/35625
摘要： A flip-flop may include a first master stage for latching data, a second slave stage for latching data, and an input multiplexer circuit receiving, as input, data to be latched in the flip-flop. The multiplexer may have single clock phase. The first master stage may be clocked based upon a clock phase, whereas the second stage may be clocked based upon another clock phase.
摘要翻译：触发器可以包括用于锁存数据的第一主级，用于锁存数据的第二从级，以及作为输入接收要锁存在触发器中的数据的输入多路复用器电路。复用器可以具有单个时钟相位。第一主级可以基于时钟相位来计时，而第二级可以基于另一个时钟相位来计时。

5. 发明授权

US08867264B2 SRAM read-write memory cell having ten transistors 有权
标题翻译：具有十个晶体管的SRAM读写存储单元
公开(公告)号：US08867264B2
公开(公告)日：2014-10-21
申请号：US13578261
申请日：2011-02-14
申请人： Fady Abouzeid , Sylvain Clerc
发明人： Fady Abouzeid , Sylvain Clerc
IPC分类号： G11C11/00
CPC分类号： G11C11/412 , G11C11/413
摘要： A device and a method for controlling an SRAM-type device, including: a bistable circuit and two switching circuits respectively connecting two access terminals of the bistable circuit to two complementary bit lines in a first direction, each switching circuit including a first switch and a second switch in series between one of the bit lines and one of the access terminals, the control terminal of the second switch being connected to a word control line in the first direction; and a third switch between the midpoint of the series connection and a terminal of application of a reference potential, a control terminal of the third switch being connected to the other one of the access terminals.
摘要翻译：一种用于控制SRAM型器件的器件和方法，包括：双稳态电路和两个开关电路，分别将双稳态电路的两个接入端连接到第一方向上的两个互补位线，每个开关电路包括第一开关和第二开关串联在一个位线和一个接入端之间，第二开关的控制端在第一方向连接到字控制线; 以及在所述串联连接的中点和施加参考电位的终端之间的第三开关，所述第三开关的控制端连接到所述另一个所述接入终端。

6. 发明申请

US20130051131A1 SRAM READ-WRITE MEMORY CELL HAVING TEN TRANSISTORS 有权
标题翻译：具有十个晶体管的SRAM读写存储单元
公开(公告)号：US20130051131A1
公开(公告)日：2013-02-28
申请号：US13578261
申请日：2011-02-14
申请人： Fady Abouzeid , Sylvain Clerc
发明人： Fady Abouzeid , Sylvain Clerc
IPC分类号： G11C11/00
CPC分类号： G11C11/412 , G11C11/413
摘要： A device and a method for controlling an SRAM-type device, including: a bistable circuit and two switching circuits respectively connecting two access terminals of the bistable circuit to two complementary bit lines in a first direction, each switching circuit including a first switch and a second switch in series between one of the bit lines and one of the access terminals, the control terminal of the second switch being connected to a word control line in the first direction; and a third switch between the midpoint of the series connection and a terminal of application of a reference potential, a control terminal of the third switch being connected to the other one of the access terminals.
摘要翻译：一种用于控制SRAM型器件的器件和方法，包括：双稳态电路和两个开关电路，分别将双稳态电路的两个接入端连接到第一方向上的两个互补位线，每个开关电路包括第一开关和第二开关串联在一个位线和一个接入端之间，第二开关的控制端在第一方向连接到字控制线; 以及在所述串联连接的中点和施加参考电位的终端之间的第三开关，所述第三开关的控制端连接到所述另一个所述接入终端。

7. 发明申请

US20110084748A1 FLIP-FLOP WITH SINGLE CLOCK PHASE AND WITH REDUCED DYNAMIC POWER 有权
标题翻译：具有单时钟相位和降低动态功率的FLIP-FLOP
公开(公告)号：US20110084748A1
公开(公告)日：2011-04-14
申请号：US12900147
申请日：2010-10-07
申请人： Fabian Firmin , Sylvain Clerc , Jean-Pierre Schoellkopf , Fady Abouzeid
发明人： Fabian Firmin , Sylvain Clerc , Jean-Pierre Schoellkopf , Fady Abouzeid
IPC分类号： H03K3/289
CPC分类号： H03K3/0372 , H03K3/356156 , H03K3/35625
摘要： A flip-flop may include a first master stage for latching data, a second slave stage for latching data, and an input multiplexer circuit receiving, as input, data to be latched in the flip-flop. The multiplexer may have single clock phase. The first master stage may be clocked based upon a clock phase, whereas the second stage may be clocked based upon another clock phase.
摘要翻译：触发器可以包括用于锁存数据的第一主级，用于锁存数据的第二从级，以及作为输入接收要锁存在触发器中的数据的输入多路复用器电路。复用器可以具有单个时钟相位。第一主级可以基于时钟相位来计时，而第二级可以基于另一个时钟相位来计时。

8. 发明申请

US20110291696A1 Method for Protecting a Logic Circuit Against External Radiation and Associated Electronic Device 有权
标题翻译：保护逻辑电路免受外部辐射和相关电子设备的方法
公开(公告)号：US20110291696A1
公开(公告)日：2011-12-01
申请号：US13111756
申请日：2011-05-19
申请人： Sylvain Clerc , Fabian Firmin , Philippe Roche
发明人： Sylvain Clerc , Fabian Firmin , Philippe Roche
IPC分类号： H03K19/00
CPC分类号： H03K19/23
摘要： A method for protecting an electronic circuit having at least one output against external radiation includes functionally duplicating the electronic circuit and linking the outputs of the electronic circuit and the duplicated electronic circuit to homologous inputs of at least functionally equivalent combinatorial or sequential elements. The homologous outputs of all the combinatorial or sequential elements are linked together. The electronic circuit can be duplicated multiple times.
摘要翻译：一种用于保护具有不受外部辐射的至少一个输出的电子电路的方法包括功能上复制电子电路并将电子电路的输出和复制的电子电路链接到至少功能上等效的组合或顺序元件的同源输入。所有组合或顺序元件的同源输出连接在一起。电子电路可以重复多次。

9. 发明授权

US08570060B2 Method for protecting a logic circuit against external radiation and associated electronic device 有权
标题翻译：保护逻辑电路免受外部辐射和相关电子设备的方法
公开(公告)号：US08570060B2
公开(公告)日：2013-10-29
申请号：US13111756
申请日：2011-05-19
申请人： Sylvain Clerc , Fabian Firmin , Philippe Roche
发明人： Sylvain Clerc , Fabian Firmin , Philippe Roche
IPC分类号： H03K19/003
CPC分类号： H03K19/23
摘要： A method for protecting an electronic circuit having at least one output against external radiation includes functionally duplicating the electronic circuit and linking the outputs of the electronic circuit and the duplicated electronic circuit to homologous inputs of at least functionally equivalent combinatorial or sequential elements. The homologous outputs of all the combinatorial or sequential elements are linked together. The electronic circuit can be duplicated multiple times.
摘要翻译：一种用于保护具有不受外部辐射的至少一个输出的电子电路的方法包括功能上复制电子电路并将电子电路的输出和复制的电子电路链接到至少功能上等效的组合或顺序元件的同源输入。所有组合或顺序元件的同源输出连接在一起。电子电路可以重复多次。

10. 发明授权

US07321506B2 Multivibrator protected against current or voltage spikes 有权
标题翻译：多谐振荡器可防止电流或电压尖峰
公开(公告)号：US07321506B2
公开(公告)日：2008-01-22
申请号：US11379720
申请日：2006-04-21
申请人： Philippe Roche , Francois Jacquet , Sylvain Clerc
发明人： Philippe Roche , Francois Jacquet , Sylvain Clerc
IPC分类号： G11C11/41
CPC分类号： H03K3/02335 , H03K3/0375
摘要： The multivibrator is protected against current or voltage spikes and includes a first data transfer port that receives, as input, multivibrator input data, and a first/master latch cell connected on the output side of the first transfer port. A second/slave latch cell is included, and a second data transfer port is placed between the first and second latch cells. Each latch cell includes a set of redundant data storage nodes. The transfer ports each circuits/devices for writing data separately into each storage node.
摘要翻译：多谐振荡器被保护以防止电流或电压尖峰，并且包括第一数据传输端口，其接收作为输入的多谐振荡器输入数据，以及连接在第一传输端口的输出侧的第一/主机锁存单元。包括第二/从属锁存单元，并且第二数据传送端口被放置在第一和第二锁存单元之间。每个锁存单元包含一组冗余数据存储节点。传输端口每个电路/用于将数据单独写入每个存储节点的设备。

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