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1. 发明授权

US6122320A Circuit for motion estimation in digitized video sequence encoders 有权
标题翻译：数字化视频序列编码器运动估计电路
公开(公告)号：US6122320A
公开(公告)日：2000-09-19
申请号：US180781
申请日：1998-11-13
申请人： Fabio Bellifemine , Gianmario Bollano , Andrea Finotello , Marco Gandini , Pierangelo Garino , Mauro Marchisio , Alessandro Torielli , Didier Nicoulaz , Stephanie Dogimont , Martin Gumm , Marco Mattavelli , Frederich Mombers
发明人： Fabio Bellifemine , Gianmario Bollano , Andrea Finotello , Marco Gandini , Pierangelo Garino , Mauro Marchisio , Alessandro Torielli , Didier Nicoulaz , Stephanie Dogimont , Martin Gumm , Marco Mattavelli , Frederich Mombers
IPC分类号： H04N7/32 , G01R31/3185 , H04N7/26 , H04N7/36 , H04N5/262
CPC分类号： G01R31/318533 , H04N19/43 , H04N19/51 , H04N19/56
摘要： The circuit for motion estimation in digitised video sequence encoders comprises at least an integrated circuit component (IM, IM1 . . . IMn) which is arranged to perform either the function of determining motion vectors and associated costs for different prediction modes, or the function of vector refinement, possibly in addition to prediction mode selection. The circuit (IM) is based on the use of two operating units (M1, M2) which are arranged to concurrently process in different ways different pixel groups according to a MIMD technique. Preferably, when the circuit performs motion vector determination, the operating units (M1, M2) are programmed to execute a genetic algorithm exploiting an initial vector population taking into account the temporal and spatial correlations in the picture.
摘要翻译： PCT No.PCT / EP98 / 01433 Sec。 371日期：1998年11月13日 102（e）日期1998年11月13日PCT 1998年3月12日PCT PCT。公开号WO98 / 42137 日期1998年9月24日数字化视频序列编码器中的运动估计电路至少包括集成电路部件（IM，IM1，... IMn），其被设置为执行用于确定不同预测模式的运动矢量和相关成本的功能，或矢量细化的功能，可能除了预测模式选择之外。电路（IM）基于使用两个操作单元（M1，M2），其被布置为根据MIMD技术以不同的方式同时处理不同的像素组。优选地，当电路执行运动矢量确定时，操作单元（M1，M2）被编程为执行利用初始矢量群体的遗传算法，其考虑了图像中的时间和空间相关性。

2. 发明授权

US5903310A Device for manipulating compressed video sequences 失效
标题翻译：用于操纵压缩视频序列的装置
公开(公告)号：US5903310A
公开(公告)日：1999-05-11
申请号：US780169
申请日：1996-12-26
申请人： Andrea Finotello , Marco Gandini , Pierangelo Garino , Mauro Marchisio
发明人： Andrea Finotello , Marco Gandini , Pierangelo Garino , Mauro Marchisio
IPC分类号： H04N7/30 , H03M7/30 , H03M7/36 , H04N7/26 , H04N7/32 , H04N7/50 , H04N7/12
CPC分类号： H04N19/85 , H04N19/42 , H04N19/423 , H04N19/46 , H04N19/61
摘要： An integrated circuit for manipulating digitized video sequences is provided, for use in a system for transmission and reception of compressed video sequences to perform, possibly with the aid of an external memory, reordering, format conversion, prediction and motion compensation on the pictures in a sequence. The device has memory for temporarily storing sequences to be manipulated and data read from the external memory; a circuit for decoding information about the manipulations to be performed; address circuitry for transferring the data between the device and the external memory; circuitry for configuring the device by means of a remote processing unit; circuitry for processing the data read from the external memory; and circuitry for arranging the output sequences in the format required by the function to be performed. A controller may control, supervise and set up the functions to be performed.
摘要翻译：提供了一种用于操纵数字化视频序列的集成电路，用于在压缩视频序列的传输和接收系统中，可能借助于外部存储器来执行重新排序，格式转换，预测和运动补偿序列。该设备具有用于临时存储要被操纵的序列和从外部存储器读取数据的存储器; 用于解码关于要执行的操作的信息的电路; 用于在设备和外部存储器之间传送数据的地址电路; 用于通过远程处理单元配置设备的电路; 用于处理从外部存储器读取的数据的电路; 以及用于以要执行的功能所需的格式布置输出序列的电路。控制器可以控制，监督和设置要执行的功能。

3. 发明授权

US5319447A Video control circuit for multimedia applications with video signal synchronizer memory 失效
标题翻译：具有视频信号同步器存储器的多媒体应用的视频控制电路
公开(公告)号：US5319447A
公开(公告)日：1994-06-07
申请号：US16686
申请日：1993-02-11
申请人： Pierangelo Garino , Giovanni Ghigo , Mauro Marchisio , Giovanni Pucci , Alfredo Rinaudo
发明人： Pierangelo Garino , Giovanni Ghigo , Mauro Marchisio , Giovanni Pucci , Alfredo Rinaudo
IPC分类号： H04N1/46 , H04N1/387 , H04N9/64 , H04N9/75 , H04N9/67 , H04N9/77
CPC分类号： H04N21/4143 , H04N9/641
摘要： The video control circuit is particularly adapted to multimedia applicati, wherein image transmission services are offered in addition to usual telephone speech and data transmission services. The circuit is capable of processing both photographic and graphic video images, satisfying both the relevant CCIR standards and the specifications proper to personal computers, VGA EGA, etc. so as to allow the representation of either types of images on an only type of display. To this end, it generates both timings proper to the CCIR standards, for a resolution of 720 columns per 480 lines, with an upper representation limit of graphic planes of 1024 columns per 1024 lines.
摘要翻译：视频控制电路特别适用于多媒体应用，除了通常的电话语音和数据传输服务外，提供图像传输服务。该电路能够处理照相和图形视频图像，满足相关的CCIR标准和适用于个人计算机，VGA EGA等的规范，以便允许在唯一类型的显示器上表示任一类型的图像。为此，它会产生适合于CCIR标准的时间，每480行分辨率为720列，每1024行1024列的图形平面上限。

4. 发明授权

US5309449A Electronic circuit for generating error detection codes for digital signals 失效
标题翻译：用于产生数字信号的检错码的电子电路
公开(公告)号：US5309449A
公开(公告)日：1994-05-03
申请号：US658219
申请日：1991-02-20
申请人： Marco Gandini , Giovanni Ghigo , Mauro Marchisio
发明人： Marco Gandini , Giovanni Ghigo , Mauro Marchisio
IPC分类号： G06F11/10 , H03M13/00 , H03M13/15
CPC分类号： H03M13/15
摘要： An electronic circuit for generating error detection codes in digital sigs organized into serial data blocks, which derives the error code from the coefficients of a remainder polynomial obtained from the division of a dividend polynomial, whose coefficients are the bits of each serial block, and a convenient divisor polynomial. The circuit has a shift register wherein at the beginning of each serial data block the reset and the first datum load are performed in a single clock interval.
摘要翻译：一种用于产生组织成串行数据块的数字信号中的错误检测码的电子电路，其从系数是每个串行块的位的除法多项式的除法获得的余数多项式的系数中导出错误代码，以及方便除数多项式。该电路具有移位寄存器，其中在每个串行数据块的开头，复位和第一基准负载在单个时钟间隔内执行。

5. 发明授权

US5197083A Multimedia protocol interface for 64 kbit/s data flow 失效
标题翻译：用于64 KBIT / S数据流的多媒体协议接口
公开(公告)号：US5197083A
公开(公告)日：1993-03-23
申请号：US619307
申请日：1990-11-28
申请人： Marco Gandini , Giovanni Ghigo , Mauro Marchisio
发明人： Marco Gandini , Giovanni Ghigo , Mauro Marchisio
IPC分类号： G06F11/10 , H04L1/00 , H04L29/08 , H04M11/06
CPC分类号： H04M11/068
摘要： A multimedia protocol interface for 64K Kbit/s data flow, organized accorg to the frame structure specified in CCITT Recommendation H221 and transmitted and received according to the standard 64 kbit/s protocol or 256 kbit/s 10 M protocol, adapted to operate autonomously or aided by an external microprocessor and has a receiver, a transmitter, a control block and circuitry for the local test of the operation of the interface itself. The external microprocessor can read both the received data and the information relevant to the receiver conditions, and can also send data to be transmitted or can read information relevant to the transmitter conditions. The receiver receives the data and clock and synchronism signals and emits at the output the received data, associated with timing signals useful for the external devices connected to the interface for data recovery. Analogously, the transmitter emits the data, receives clock an synchronism signals and supplies data and timings to the external devices. The local test is carried out by verifying whether the receiver succeeds in recovering the synchronism from the signal emitted by the transmitter if the same interface, under microprocessor supervision, and if the data are correctly transmitted and received.

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