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1. 发明授权

US11074947B2 Semiconductor memory apparatus and data processing system 有权
公开(公告)号：US11074947B2
公开(公告)日：2021-07-27
申请号：US16837564
申请日：2020-04-01
申请人： FUJITSU LIMITED
发明人： Yuichiro Ajima , Toshiyuki Shimizu
IPC分类号： G11C5/04 , G11C5/06 , G11C7/10 , G11C29/44
摘要： A semiconductor memory apparatus includes a plurality of memory dies and a logic die, which are stacked to each other. The logic die includes a memory interface for a memory apparatus to be coupled to the semiconductor memory apparatus, and a switch coupled to a plurality of channels included in a control device which controls the semiconductor memory apparatus. The switch includes a first switch element which couples one of the plurality of channels to the memory interface or one of the plurality of memory dies, and a second switch element which couples another one of the plurality of channels to another one of the plurality of memory dies. Even if some memory dies are defective, the semiconductor memory apparatus is capable to operate.

2. 发明申请

US20190324927A1 PROCESSOR AND INFORMATION PROCESSING APPARATUS 审中-公开
公开(公告)号：US20190324927A1
公开(公告)日：2019-10-24
申请号：US16360069
申请日：2019-03-21
申请人： FUJITSU LIMITED
发明人： Yuichiro Ajima , Shinya Hiramoto , YUJI KONDO
IPC分类号： G06F13/16 , G06F3/06 , G06F13/40
摘要： A processor includes: a plurality of processor cores; an interconnector including a reduction operation device and configured to communicate with another processor; a memory controller configured to control a main memory; a bus configured to couple the plurality of processor cores, the interconnector, and the memory controller to each other; and a reduction operation buffer coupled to the bus and the interconnector, wherein each of the processor cores writes control information to control the reduction operation device included in the interconnector and a value to be operated by the reduction operation device in the reduction operation buffer, and the interconnector reads out the control information and the value from the reduction operation buffer and delivers the control information and the value to the reduction operation device.

3. 发明申请

US20190073247A1 COMPUTATION NODE DEVICE, PARALLEL COMPUTER SYSTEM, AND CONTROL METHOD FOR COMPUTATION NODE DEVICE 审中-公开
公开(公告)号：US20190073247A1
公开(公告)日：2019-03-07
申请号：US16055828
申请日：2018-08-06
申请人： FUJITSU LIMITED
发明人： YUJI KONDO , Shinya Hiramoto , Yuichiro Ajima
IPC分类号： G06F9/52 , H04L1/00 , H03M13/09
CPC分类号： G06F9/522 , H03M13/09 , H03M13/091 , H04L1/0052 , H04L1/0061
摘要： A computation node device includes a buffer configured to store first data, a receiver configured to receive a packet including second data, an error check circuit configured to perform an error check of the packet and output a check result, and an operation device configured to perform, before receiving the check result output from the error check circuit, a reduction operation by using the first data stored in the buffer and the second data included in the packet and output an operation result of the reduction operation when the check result output from the error check circuit indicates non-existence of an error in the packet.

4. 发明授权

US09385961B2 Parallel computing device, communication control device, and communication control method 有权
标题翻译：并行计算设备，通信控制设备和通信控制方法
公开(公告)号：US09385961B2
公开(公告)日：2016-07-05
申请号：US14031775
申请日：2013-09-19
申请人： FUJITSU LIMITED
发明人： Shinya Hiramoto , Yuji Oinaga , Yuichiro Ajima , Tomohiro Inoue
IPC分类号： H04J3/16 , H04L12/805 , H04L12/825 , G06F15/173
CPC分类号： H04L47/365 , G06F15/173 , H04L47/25
摘要： A parallel computing device includes a plurality of communicatively interconnected nodes for executing an arithmetic process. Each of the plurality of nodes includes: a measurement unit configured to measure a communication bandwidth up to a destination node based on a communication scheme among the nodes, and a control unit configured to control a size of a packet transmitted to the destination node according to the communication bandwidth measured by the measurement unit.
摘要翻译：并行计算设备包括用于执行算术处理的多个通信互连的节点。所述多个节点中的每一个包括：测量单元，被配置为基于所述节点之间的通信方案来测量直到目的地节点的通信带宽;以及控制单元，被配置为根据所述节点控制发送到所述目的地节点的分组的大小由测量单元测量的通信带宽。

5. 发明申请

US20140289300A1 PROCESSOR AND PROCESSING METHOD 有权
标题翻译：处理器和处理方法
公开(公告)号：US20140289300A1
公开(公告)日：2014-09-25
申请号：US14159728
申请日：2014-01-21
申请人： FUJITSU LIMITED
发明人： Yuichiro Ajima
IPC分类号： G06F7/57
CPC分类号： G06F7/5443
摘要： In a processor that includes a plurality of multipliers and a plurality of adders to execute matrix product processing, each data of input vector data involved in the arithmetic processing is used in two multipliers, whereby arithmetic processing of elements in different rows and different columns in a matrix product operation is executed with a single instruction, that enables the sharing of input data to reduce the number of times data are moved in the whole matrix product processing and reduce power consumption.
摘要翻译：在包括多个乘法器和多个加法器以执行矩阵乘积处理的处理器中，算术处理中涉及的输入向量数据的每个数据被用在两个乘法器中，由此在一个乘法器中的不同行和不同列中的元素的运算处理使用单个指令执行矩阵产品操作，使得能够共享输入数据以减少数据在整个矩阵产品处理中移动的次数并降低功耗。

6. 发明申请

US20140215483A1 RESOURCE-USAGE TOTALIZING METHOD, AND RESOURCE-USAGE TOTALIZING DEVICE 审中-公开
标题翻译：资源使用总计方法和资源使用总计设备
公开(公告)号：US20140215483A1
公开(公告)日：2014-07-31
申请号：US14136429
申请日：2013-12-20
申请人： FUJITSU LIMITED
发明人： Hideyuki Akimoto , Yuichiro Ajima , Kenichi Miura , Takayuki Okamoto , Tomoya Adachi , Shinji Sumimoto
IPC分类号： G06F9/50
CPC分类号： G06F9/5016 , G06F9/5022 , G06F11/3409 , G06F11/3466 , G06F11/3476 , G06F11/362 , G06F2201/88
摘要： A memory allocation/free replacing unit hooks a call of a memory allocating/freeing unit. The memory allocation/free replacing unit generates information required for totalization of a dynamically used memory amount, writes the generated information to a log file, and calls the memory allocating/freeing unit to perform memory allocation and free. A totalization processing unit loads the log file and totalizes a dynamically used memory amount for each dynamic library, for each function, or for each thread.
摘要翻译：存储器分配/空闲替换单元挂接存储器分配/释放单元的呼叫。存储器分配/自由替换单元产生用于累计动态使用的存储器量所需的信息，将生成的信息写入日志文件，并且调用存储器分配/释放单元来执行存储器分配和空闲。累加处理单元加载日志文件，并为每个动态库，每个功能或每个线程总计动态使用的内存量。

7. 发明申请

US20140023090A1 PARALLEL COMPUTING DEVICE, COMMUNICATION CONTROL DEVICE, AND COMMUNICATION CONTROL METHOD 有权
标题翻译：并行计算设备，通信控制设备和通信控制方法
公开(公告)号：US20140023090A1
公开(公告)日：2014-01-23
申请号：US14031775
申请日：2013-09-19
申请人： FUJITSU LIMITED
发明人： Shinya Hiramoto , Yuji Oinaga , Yuichiro Ajima , Tomohiro Inoue
IPC分类号： H04L12/805
CPC分类号： H04L47/365 , G06F15/173 , H04L47/25
摘要： A parallel computing device includes a plurality of communicatively interconnected nodes for executing an arithmetic process. Each of the plurality of nodes includes: a measurement unit configured to measure a communication bandwidth up to a destination node based on a communication scheme among the nodes, and a control unit configured to control a size of a packet transmitted to the destination node according to the communication bandwidth measured by the measurement unit.
摘要翻译：并行计算设备包括用于执行算术处理的多个通信互连的节点。所述多个节点中的每一个包括：测量单元，被配置为基于所述节点之间的通信方案来测量直到目的地节点的通信带宽;以及控制单元，被配置为根据所述节点控制发送到所述目的地节点的分组的大小由测量单元测量的通信带宽。

8. 发明授权

US10592299B2 Computation node device, parallel computer system, and control method for computation node device 有权
公开(公告)号：US10592299B2
公开(公告)日：2020-03-17
申请号：US16055828
申请日：2018-08-06
申请人： FUJITSU LIMITED
发明人： Yuji Kondo , Shinya Hiramoto , Yuichiro Ajima
IPC分类号： H03M13/00 , G06F9/52 , H03M13/09 , H04L1/00
摘要： A computation node device includes a buffer configured to store first data, a receiver configured to receive a packet including second data, an error check circuit configured to perform an error check of the packet and output a check result, and an operation device configured to perform, before receiving the check result output from the error check circuit, a reduction operation by using the first data stored in the buffer and the second data included in the packet and output an operation result of the reduction operation when the check result output from the error check circuit indicates non-existence of an error in the packet.

9. 发明申请

US20190334836A1 PROCESSOR AND INFORMATION PROCESSING APPARATUS 审中-公开
公开(公告)号：US20190334836A1
公开(公告)日：2019-10-31
申请号：US16387987
申请日：2019-04-18
申请人： FUJITSU LIMITED
发明人： Yuichiro Ajima , Shinya Hiramoto , YUJI KONDO
IPC分类号： H04L12/933 , H04L12/937 , H04L12/935
摘要： An information processing apparatus includes a plurality of processors and a plurality of links provided between the processors in a plurality of axis directions. Each of the processors includes a processor circuit, a memory, a memory controller, and an interconnect coupled to the processor circuit. The interconnect includes: a network switch configured to perform switching between the first links and a second link to its own processor; link counters provided to input links and output links of the first links and the second link respectively, the link counters being configured to count at least the number of packets passing through the input links and the output links; and a recorder configured to store count values of the link counters in the memory via the memory controller without a control by the processor circuit.

10. 发明授权

US10230625B2 Information processing apparatus, information processing system, and communication device 有权
公开(公告)号：US10230625B2
公开(公告)日：2019-03-12
申请号：US14924168
申请日：2015-10-27
申请人： FUJITSU LIMITED
发明人： Masahiro Maeda , Koichiro Takayama , Tomohiro Inoue , Shinya Hiramoto , Shun Ando , Yuichiro Ajima
IPC分类号： H04L12/703 , H04L12/707 , H04L12/26 , G06F13/42 , G06F11/00 , G06F11/07 , H04L1/18 , G06F15/76
摘要： An information processing apparatus including: an arithmetic processing unit; and a communication device configured to receive data from another information processing apparatus through a plurality of first lanes and to output the received data to the arithmetic processing unit, wherein the communication device includes a detection unit that detects a failure of the plurality of first lanes; and a control unit that performs a first degradation process of stopping use of any one of the plurality of first lanes, based on a degradation request, performs a restoration process of resuming use of a first lane for which use has been stopped, based on a restoration request, and performs a second degradation process of stopping use of a first lane for which use has been resumed, when the detection unit detects a failure of the first lane for which use has been resumed, in the restoration process.

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