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1. 发明申请

US20220139908A1 SEMICONDUCTOR DEVICE 有权
公开(公告)号：US20220139908A1
公开(公告)日：2022-05-05
申请号：US17577048
申请日：2022-01-17
申请人： FUJI ELECTRIC CO., LTD.
发明人： Tomoyuki OBATA , Soichi YOSHIDA , Tetsutaro IMAGAWA , Seiji MOMOTA
IPC分类号： H01L27/07 , H01L27/06 , H01L29/08 , H01L29/739
摘要： Provided is a semiconductor device having transistor and diode sections. The semiconductor device comprises: a gate metal layer provided above the upper surface of a semiconductor substrate; an emitter electrode provided above the upper surface of the semiconductor substrate; a first conductivity-type emitter region provided on the semiconductor substrate upper surface side in the transistor section; a gate trench section, which is provided on the semiconductor substrate upper surface side in the transistor section, is electrically connected to the gate metal layer, and is in contact with the emitter region; an emitter trench section, which is provided on the semiconductor substrate upper surface side in the diode section, and is electrically connected to the emitter electrode; and a dummy trench section, which is provided on the semiconductor substrate upper surface side, is electrically connected to the gate metal layer, and is not in contact with the emitter region.

2. 发明申请

US20220328668A1 SEMICONDUCTOR DEVICE 有权
公开(公告)号：US20220328668A1
公开(公告)日：2022-10-13
申请号：US17680270
申请日：2022-02-24
申请人： FUJI ELECTRIC CO., LTD.
发明人： Shigeki SATO , Soichi YOSHIDA , Kouji ASAHI , Seiji MOMOTA
IPC分类号： H01L29/739 , H01L29/423 , H01L29/06 , G01K7/01 , H01L23/528
摘要： Provided is a semiconductor device including: a first trench portion having a predetermined first trench length; a second trench portion having a second trench length longer than the first trench length; a first gate runner portion configured to be electrically connected to an end portion of the first trench portion; and a second gate runner portion configured to be electrically connected to the first gate runner portion and electrically connected to an end portion of the second trench portion. A resistivity per unit length of the first gate runner portion is larger than a resistivity per unit length of the second gate runner portion.

3. 发明申请

US20160372586A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件及制造半导体器件的方法
公开(公告)号：US20160372586A1
公开(公告)日：2016-12-22
申请号：US15250972
申请日：2016-08-30
申请人： FUJI ELECTRIC CO., LTD.
发明人： Takeshi FUJII , Seiji MOMOTA
IPC分类号： H01L29/739 , H01L29/423 , H01L29/66
CPC分类号： H01L29/7397 , H01L29/0619 , H01L29/0696 , H01L29/423 , H01L29/42368 , H01L29/42376 , H01L29/66348 , H01L29/78
摘要： In a trench deeper than a thickness of a p-type base layer and configured by a first trench and a second trench, a second trench positioned at a lower portion is configured by a third trench and a fourth trench. A width of the second trench along an X direction is expanded more than the first trench positioned above the second trench. Along the X direction, the extent to which the second trench is expanded differs for the third trench and the fourth trench. Thus, a width of the lower portion of the trench differs along a Y direction, enabling reduced gate capacitance compared to uniform expansion along a transverse direction of the trench. Further, ON voltage may be reduced and switching capability may be improved.
摘要翻译：在比p型基底层的厚度更深的并且由第一沟槽和第二沟槽构成的沟槽中，位于下部的第二沟槽由第三沟槽和第四沟槽构成。沿着X方向的第二沟槽的宽度比位于第二沟槽上方的第一沟槽更大。沿X方向，第二沟槽的膨胀程度对于第三沟槽和第四沟槽而言是不同的。因此，沿着Y方向，沟槽的下部的宽度不同，与沿着沟槽的横向的均匀膨胀相比，能够减小栅极电容。此外，可以降低ON电压并且可以提高开关能力。

4. 发明申请

US20140159107A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20140159107A1
公开(公告)日：2014-06-12
申请号：US14176610
申请日：2014-02-10
申请人： FUJI ELECTRIC CO., LTD.
发明人： Naoko KURATA , Seiji MOMOTA , Hitoshi ABE
IPC分类号： H01L29/739
CPC分类号： H01L29/7397 , H01L29/0615 , H01L29/0619 , H01L29/0696 , H01L29/404 , H01L29/407 , H01L29/42368
摘要： Some aspects of the invention include a trench gate structure including a p base layer, an n+ emitter region, a trench, a gate oxide film, and a doped polysilicon gate electrode is provided in an active region. A p-type extension region formed by extending the p base layer to an edge termination structure region can be provided in the circumference of a plurality of trenches. One or more annular outer trenches which are formed at the same time as the plurality of trenches are provided in the p-type extension region. The annular outer trenches can surround all of the trenches. A second gap between the annular outer trench and the outermost trench or between adjacent annular outer trenches is less than a first gap between adjacent trenches.
摘要翻译：本发明的一些方面包括在有源区域中设置包括p基极层，n +发射极区域，沟槽，栅极氧化物膜和掺杂多晶硅栅电极的沟槽栅极结构。通过将p基底层延伸到边缘终端结构区域形成的p型延伸区域可以设置在多个沟槽的圆周中。在p型延伸区域中设置与多个沟槽同时形成的一个或多个环形外沟槽。环形外沟槽可围绕所有的沟槽。环形外沟槽和最外层沟槽之间或相邻环形外沟槽之间的第二间隙小于相邻沟槽之间的第一间隙。

5. 发明申请

US20190267370A1 SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：US20190267370A1
公开(公告)日：2019-08-29
申请号：US16228803
申请日：2018-12-21
申请人： FUJI ELECTRIC CO., LTD.
发明人： Shigeki SATO , Seiji MOMOTA , Tadashi MIYASAKA
IPC分类号： H01L27/07 , H01L29/10 , H01L29/739 , H01L29/861 , H01L29/417 , H01L29/08 , H01L29/423
摘要： A semiconductor device is preferably excellent in characteristics such as a loss characteristic. Provided is a semiconductor device including a semiconductor substrate, including an upper-surface electrode provided on an upper surface of the semiconductor substrate; an lower-surface electrode provided on a lower surface of the semiconductor substrate; a transistor portion provided in the semiconductor substrate and connected to the upper-surface electrode and the lower-surface electrode; a first diode portion provided in the semiconductor substrate and connected to the upper-surface electrode and the lower-surface electrode; and a second diode portion provided in the semiconductor substrate and connected to the upper-surface electrode and the lower-surface electrode, wherein the first diode portion and the second diode portion have different resistivities in a depth direction of the semiconductor substrate.

6. 发明申请

US20160036316A1 INSULATED GATE SEMICONDUCTOR DEVICE 有权
标题翻译：绝缘栅半导体器件
公开(公告)号：US20160036316A1
公开(公告)日：2016-02-04
申请号：US14879553
申请日：2015-10-09
申请人： FUJI ELECTRIC CO., LTD.
发明人： Seiji MOMOTA
IPC分类号： H02M1/088 , H03K17/082 , H02M7/5387
CPC分类号： H02M1/088 , H02M1/08 , H02M7/00 , H02M7/21 , H02M7/5387 , H02M7/53871 , H03K17/06 , H03K17/0828 , H03K2017/0806
摘要： An insulated gate semiconductor device includes an insulated gate semiconductor element, an output current detection unit, a voltage detection unit, and a heat generation amount suppression unit. The insulated gate semiconductor element on-operates by receiving a first gate voltage at a control terminal, and switches and outputs an input voltage to a load. The output current detection unit detects an output current to the load. The voltage detection unit detects an on-voltage of the insulated gate semiconductor element. The heat generation amount suppression unit sets a gate voltage to be applied to the control terminal of the insulated gate semiconductor element higher than the first gate voltage in response to the output current exceeding a rated current value and the on-voltage being lower than a first threshold voltage.
摘要翻译：绝缘栅半导体器件包括绝缘栅半导体元件，输出电流检测单元，电压检测单元和发热量抑制单元。绝缘栅极半导体元件通过在控制端子处接收第一栅极电压而工作，并且将输入电压切换并输出到负载。输出电流检测单元检测到负载的输出电流。电压检测单元检测绝缘栅半导体元件的导通电压。发热量抑制单元响应于超过额定电流值的输出电流设定施加到绝缘栅极半导体元件的控制端子的栅极电压，该栅极电压高于第一栅极电压，并且导通电压低于第一栅极电压阈值电压。

7. 发明公开

US20240145465A1 SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：US20240145465A1
公开(公告)日：2024-05-02
申请号：US18539311
申请日：2023-12-14
申请人： FUJI ELECTRIC CO., LTD.
发明人： Shigeki SATO , Seiji MOMOTA , Tadashi MIYASAKA
IPC分类号： H01L27/07 , H01L29/06 , H01L29/08 , H01L29/10 , H01L29/32 , H01L29/417 , H01L29/423 , H01L29/739 , H01L29/861
CPC分类号： H01L27/0716 , H01L29/0615 , H01L29/0657 , H01L29/0847 , H01L29/1095 , H01L29/32 , H01L29/41708 , H01L29/4236 , H01L29/7397 , H01L29/8611 , H01L29/8613 , H01L29/407
摘要： A semiconductor device is preferably excellent in characteristics such as a loss characteristic. Provided is a semiconductor device including a semiconductor substrate, including an upper-surface electrode provided on an upper surface of the semiconductor substrate; an lower-surface electrode provided on a lower surface of the semiconductor substrate; a transistor portion provided in the semiconductor substrate and connected to the upper-surface electrode and the lower-surface electrode; a first diode portion provided in the semiconductor substrate and connected to the upper-surface electrode and the lower-surface electrode; and a second diode portion provided in the semiconductor substrate and connected to the upper-surface electrode and the lower-surface electrode, wherein the first diode portion and the second diode portion have different resistivities in a depth direction of the semiconductor substrate.

8. 发明公开

US20240128320A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD 审中-公开
公开(公告)号：US20240128320A1
公开(公告)日：2024-04-18
申请号：US18542812
申请日：2023-12-18
申请人： FUJI ELECTRIC CO., LTD.
发明人： Shuntaro YAGUCHI , Hiroshi TAKISHITA , Seiji MOMOTA
IPC分类号： H01L29/08 , H01L21/265 , H01L27/06 , H01L29/06 , H01L29/739 , H01L29/861
CPC分类号： H01L29/0834 , H01L21/26513 , H01L27/0664 , H01L29/0638 , H01L29/7397 , H01L29/8613
摘要： Provided is a semiconductor device in which a doping concentration peak of a buffer region has a local maximum at which a doping concentration shows a local maximum value, a lower tail in which the doping concentration monotonously decreases from the local maximum toward a lower surface, and an upper tail in which the doping concentration monotonously decreases from the local maximum toward an upper surface, and at least one of the doping concentration peaks of the buffer region is a gradual concentration peak in which a slope ratio obtained by dividing an absolute value of a slope of the upper tail by an absolute value of a slope of the lower tail is 0.1 or more and 3 or less.

9. 发明公开

US20240021607A1 SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：US20240021607A1
公开(公告)日：2024-01-18
申请号：US18476284
申请日：2023-09-27
申请人： FUJI ELECTRIC CO., LTD.
发明人： Tomoyuki OBATA , Soichi YOSHIDA , Tetsutaro IMAGAWA , Seiji MOMOTA
IPC分类号： H01L27/07 , H01L27/06 , H01L29/08 , H01L29/739
CPC分类号： H01L27/0727 , H01L27/0664 , H01L29/0804 , H01L29/7391
摘要： Provided is a semiconductor device having transistor and diode sections. The semiconductor device comprises: a gate metal layer provided above the upper surface of a semiconductor substrate; an emitter electrode provided above the upper surface of the semiconductor substrate; a first conductivity-type emitter region provided on the semiconductor substrate upper surface side in the transistor section; a gate trench section, which is provided on the semiconductor substrate upper surface side in the transistor section, is electrically connected to the gate metal layer, and is in contact with the emitter region; an emitter trench section, which is provided on the semiconductor substrate upper surface side in the diode section, and is electrically connected to the emitter electrode; and a dummy trench section, which is provided on the semiconductor substrate upper surface side, is electrically connected to the gate metal layer, and is not in contact with the emitter region.

10. 发明申请

US20140210037A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20140210037A1
公开(公告)日：2014-07-31
申请号：US14154778
申请日：2014-01-14
申请人： FUJI ELECTRIC CO., LTD.
发明人： Seiji MOMOTA
IPC分类号： H01L29/872
CPC分类号： H01L29/402 , H01L29/0615 , H01L29/8611
摘要： A power diode is disclosed wherein it is possible to lower on-voltage by expanding a conducting region at an on time. By applying negative voltage to a plate electrode when turning on a power diode, an inversion layer is formed in a front surface layer of an n drift region sandwiched between a p guard ring region and a p anode region, and the p guard ring region and p anode region are connected by the inversion layer, thereby causing one portion or all of the p guard ring region to function as an active region together with the anode region, and expanding an energization region, thus lowering on-voltage.
摘要翻译：公开了一种功率二极管，其中可以通过在导通时间上扩展导电区域来降低导通电压。通过在接通功率二极管时向平板电极施加负电压，在夹在p保护环区域和ap阳极区域之间的n漂移区域的前表面层中形成反型层，并且p保护环区域和p阳极区域通过反转层连接，从而使p保护环区域的一部分或全部与阳极区域一起用作有源区，并且扩大通电区域，从而降低导通电压。

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