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1. 发明申请

US20220239404A1 SENSITIVITY OF BLUETOOTH RECEIVER BY INTRODUCING INTERLEAVER 有权
公开(公告)号：US20220239404A1
公开(公告)日：2022-07-28
申请号：US17157170
申请日：2021-01-25
申请人： Fudan University
发明人： Yi Jiang , Jie Yang , Qinghe Du , Rui Wang , Wei Zhang , Fengjie Li
IPC分类号： H04L1/00 , H04W4/80
摘要： The invention belongs to the field of low-power consumption Bluetooth technology in wireless communication, in particular to a method for improving the sensitivity of the receiver in a low-power consumption Bluetooth system. The method of the invention is to introduce a deinterleaver between the symbol pattern mapper and GFSK modulator of the transmitting terminal under the low-power consumption Bluetooth coding mode, which is used to perform additional processing on the bitstream data and then perform modulation; then, due to the introduction of interleaving, Turbo iterative processing of demodulation and decoding can be performed at the receiving terminal; the receiving terminal comprises a Turbo iterative demodulator and decoder, which is used to model the low-power consumption Bluetooth GFSK modulator and convolutional coder into finite state machines, and then combine the deinterleaver to use the BCJR algorithm for iterative demodulation and decoding.

2. 发明授权

US11011534B2 Multi-level cell thin-film transistor memory and method of fabricating the same 有权
公开(公告)号：US11011534B2
公开(公告)日：2021-05-18
申请号：US16482121
申请日：2017-12-29
申请人： FUDAN UNIVERSITY
发明人： Shijin Ding , Shibing Qian , Wenjun Liu , Wei Zhang
IPC分类号： H01L27/11568 , H01L29/423 , H01L21/28 , G11C11/56 , G11C16/04 , G11C16/10 , G11C16/14 , H01L21/02 , H01L21/027 , H01L21/465 , H01L21/4763 , H01L29/24 , H01L29/45 , H01L29/51 , H01L29/66 , H01L29/786 , H01L29/792
摘要： A multi-level cell thin-film transistor memory and a method of fabricating the same, a structure of which memory comprises sequentially from down to top: a gate electrode, a charge blocking layer, a charge trapping layer, a charge tunneling layer, an active region, and source and drain electrodes; wherein the charge tunneling layer fully encloses the charge trapping layer so as to completely isolate the charge trapping layer from the ambience, which prevents change of physical properties and chemical compositions of the charge trapping layer during the annealing treatment, reduces loss of charges stored in the charge trapping layer, and enhances data retention property and device performance stability; a metal oxide semiconductor thin film is utilized as the charge trapping layer of the memory, which implements multi-level cell storage and improves storage density.

3. 发明申请

US20140284728A1 Metal Silicide Thin Film, Ultra-Shallow Junctions, Semiconductor Device and Method of Making 有权
标题翻译：金属硅化物薄膜，超浅接头，半导体器件及其制造方法
公开(公告)号：US20140284728A1
公开(公告)日：2014-09-25
申请号：US13704601
申请日：2012-12-12
申请人： Fudan University
发明人： Dongping Wu , Peng Xu , Wei Zhang , Shi-Li Zhang
IPC分类号： H01L21/285 , H01L29/66 , H01L29/786
CPC分类号： H01L21/28518 , H01L21/2855 , H01L21/324 , H01L29/665 , H01L29/66575 , H01L29/66643 , H01L29/66742 , H01L29/786
摘要： A metal silicide thin film and ultra-shallow junctions and methods of making are disclosed. In the present disclosure, by using a metal and semiconductor dopant mixture as a target, a mixture film is formed on a semiconductor substrate using a physical vapor deposition (PVD) process. The mixture film is removed afterwards by wet etching, which is followed by annealing to form metal silicide thin film and ultra-shallow junctions. Because the metal and semiconductor dopant mixture is used as a target to deposit the mixture film, and the mixture film is removed by wet etching before annealing, self-limiting, ultra-thin, and uniform metal silicide film and ultra-shallow junctions are formed concurrently in semiconductor field-effect transistor fabrication processes, which are suitable for field-effect transistors at the 14 nm, 11 nm, or even further technology node.
摘要翻译：公开了一种金属硅化物薄膜和超浅结的制造方法。在本公开中，通过使用金属和半导体掺杂剂混合物作为靶，使用物理气相沉积（PVD）工艺在半导体衬底上形成混合膜。然后通过湿蚀刻除去混合物膜，随后退火以形成金属硅化物薄膜和超浅结。由于金属和半导体掺杂剂混合物用作沉积混合物膜的靶，并且在退火之前通过湿蚀刻除去混合物膜，形成自限制，超薄且均匀的金属硅化物膜和超浅结同时在半导体场效应晶体管制造工艺中，其适用于14nm，11nm甚至更进一步的技术节点处的场效应晶体管。

4. 发明申请

US20140252359A1 Semiconductor Device and Method of Making 有权
标题翻译：半导体器件及制造方法
公开(公告)号：US20140252359A1
公开(公告)日：2014-09-11
申请号：US13704614
申请日：2012-12-14
申请人： Fudan University
发明人： Dongping Wu , Zhaoyang Pi , Na Zhao , Wei Zhang , Shi-Li Zhang
IPC分类号： H01L21/48 , H01L21/768 , H01L29/45
CPC分类号： H01L21/486 , H01L21/76843 , H01L21/76855 , H01L21/76883 , H01L21/76889 , H01L23/485 , H01L23/53271 , H01L29/458 , H01L2924/0002 , H01L2924/00
摘要： The present disclosure is related to semiconductor technologies and discloses a semiconductor device and its method of making. In the present disclosure, a transistor's source and drain are led out by forming vias or contact holes in an insulator layer covering the transistor and at metal silicide contact regions corresponding to the source and drain, and by filling the vias with metal-semiconductor compound. Because the metal-semiconductor compound has relatively low resistivity, the resistance of the material in the vias can be minimized. Also, because the material used to fill the vias and the material forming the source/drain contact regions are both metal-semiconductor compound, contact resistance between the material filling the vias and the source/drain contact regions can be minimized. Furthermore, because the material filling the vias is metal-semiconductor compound, the conducting material in the vias and dielectric material in the insulator layer can form good interface and have good adhesion properties, and the conducting material would not cause structural damage in the dielectric material. Thus, there is no need to form a barrier layer between the insulator layer and the material filling the vias.
摘要翻译：本公开涉及半导体技术，并公开了一种半导体器件及其制造方法。在本公开内容中，通过在覆盖晶体管的绝缘体层和对应于源极和漏极的金属硅化物接触区域处形成通孔或接触孔，并且通过用金属半导体化合物填充通孔来引出晶体管的源极和漏极。因为金属 - 半导体化合物具有相对较低的电阻率，所以可以使过孔中的材料的电阻最小化。此外，由于用于填充通孔的材料和形成源极/漏极接触区域的材料都是金属 - 半导体化合物，所以填充通孔的材料与源极/漏极接触区域之间的接触电阻可以最小化。此外，由于填充过孔的材料是金属 - 半导体化合物，所以绝缘体层中的通孔和电介质材料中的导电材料可以形成良好的界面并且具有良好的粘合性能，并且导电材料不会在介电材料中引起结构损坏。因此，不需要在绝缘体层和填充通孔的材料之间形成阻挡层。

5. 发明申请

US20130341697A1 TUNNEL TRANSISTOR STRUCTURE INTEGRATED WITH A RESISTANCE RANDOM ACCESS MEMORY (RRAM) AND A MANUFACTURING METHOD THEREOF 有权
标题翻译：与电阻随机存取存储器（RRAM）集成的隧道晶体管结构及其制造方法
公开(公告)号：US20130341697A1
公开(公告)日：2013-12-26
申请号：US13663180
申请日：2012-10-29
申请人： FUDAN UNIVERSITY
发明人： Xi Lin , Pengfei Wang , Qingqing Sun , Wei Zhang
IPC分类号： H01L45/00
CPC分类号： H01L45/1206 , H01L27/2436 , H01L45/04 , H01L45/1233 , H01L45/146 , H01L45/16 , H01L45/1616
摘要： The invention relates to the technical field of semiconductor memories, in particular to a tunnel transistor structure integrated with a resistance random access memory and a manufacturing method thereof. The tunnel transistor structure in the present invention comprises a semiconductor substrate, and a tunnel transistor and a resistance random access memory formed on the semiconductor substrate, wherein the gate dielectric layer of the tunnel transistor extends to the surface of a drain region of the tunnel transistor; the part of the gate dielectric layer on the surface of the drain region of the tunnel transistor forms the resistance-variable storage layer of the resistance random access memory. In this invention, the high-quality gate dielectric layer of the tunnel transistor and the resistance-variable storage layer of the resistance random access memory are obtained by primary atomic layer deposition which integrates the resistance random access memory and tunnel transistor together without increasing steps. This process is simple and can combine the shallow trench isolation or field oxygen isolation and ion implantation or diffusion of source electrode and drain electrode to make integration convenient.
摘要翻译：本发明涉及半导体存储器的技术领域，特别涉及与电阻随机存取存储器集成的隧道晶体管结构及其制造方法。本发明的隧道晶体管结构包括半导体衬底和形成在半导体衬底上的隧道晶体管和电阻随机存取存储器，其中隧道晶体管的栅介质层延伸到隧道晶体管的漏极区的表面 ; 隧道晶体管的漏极区域的表面上的栅极电介质层的一部分形成电阻随机存取存储器的电阻变化存储层。在本发明中，隧道晶体管的高质量栅极电介质层和电阻随机存取存储器的电阻可变存储层通过主要原子层沉积获得，其将电阻随机存取存储器和隧道晶体管集成在一起而不增加步骤。该工艺简单，可以结合浅沟槽隔离或场氧隔离以及源电极和漏电极的离子注入或扩散，使集成方便。

6. 发明授权

US11456818B2 Sensitivity of bluetooth receiver by introducing interleaver 有权
公开(公告)号：US11456818B2
公开(公告)日：2022-09-27
申请号：US17157170
申请日：2021-01-25
申请人： Fudan University
发明人： Yi Jiang , Jie Yang , Qinghe Du , Rui Wang , Wei Zhang , Fengjie Li
IPC分类号： H04L1/00 , H04W4/80
摘要： The invention belongs to the field of low-power consumption Bluetooth technology in wireless communication, in particular to a method for improving the sensitivity of the receiver in a low-power consumption Bluetooth system. The method of the invention is to introduce a deinterleaver between the symbol pattern mapper and GFSK modulator of the transmitting terminal under the low-power consumption Bluetooth coding mode, which is used to perform additional processing on the bitstream data and then perform modulation; then, due to the introduction of interleaving, Turbo iterative processing of demodulation and decoding can be performed at the receiving terminal; the receiving terminal comprises a Turbo iterative demodulator and decoder, which is used to model the low-power consumption Bluetooth GFSK modulator and convolutional coder into finite state machines, and then combine the deinterleaver to use the BCJR algorithm for iterative demodulation and decoding.

7. 发明申请

US20150311306A1 METAL-OXIDE-SEMICONDUCTOR (MOS) TRANSISTOR STRUCTURE INTEGRATED WITH A RESISTANCE RANDOM ACCESS MEMORY (RRAM) AND THE MANUFACTURING METHODS THEREOF 有权
标题翻译：金属氧化物半导体（MOS）晶体管结构与电阻随机存取存储器（RRAM）及其制造方法
公开(公告)号：US20150311306A1
公开(公告)日：2015-10-29
申请号：US14702228
申请日：2015-05-01
申请人： Fudan University
发明人： Xi Lin , Pengfei Wang , Qingqing Sun , Wei Zhang
IPC分类号： H01L29/51 , H01L45/00 , H01L21/283 , H01L21/306 , H01L27/24 , H01L29/66
CPC分类号： H01L29/51 , G11C13/0002 , H01L21/283 , H01L21/30604 , H01L27/2436 , H01L29/66477 , H01L45/04 , H01L45/1206 , H01L45/1226 , H01L45/1233 , H01L45/146 , H01L45/16 , H01L45/1616
摘要： The present invention belongs to the technical field of semiconductor memories, in particular to a metal oxide semiconductor (MOS) transistor structure integrated with a resistance random access memory (RRAM). The MOS transistor structure comprises a MOS transistor and a RRAM formed on a substrate, wherein a gate dielectric layer of said MOS transistor extends to the surface of a drain region of said MOS transistor; and the part of the gate dielectric layer on the surface of the drain region of said MOS transistor forms a resistance-variable storage layer of said RRAM. In this invention, the high-quality dielectric layer of the MOS transistor and the resistance-variable storage layer of the RRAM are obtained by primary atomic layer deposition which integrates the RRAM and MOS transistor together without increasing steps. This process is simple and can combine the shallow trench isolation or field oxygen isolation and ion implantation or diffusion of source electrode and drain electrode to make integration convenient.
摘要翻译：本发明属于半导体存储器的技术领域，特别涉及与电阻随机存取存储器（RRAM）集成的金属氧化物半导体（MOS）晶体管结构。 MOS晶体管结构包括形成在衬底上的MOS晶体管和RRAM，其中所述MOS晶体管的栅介质层延伸到所述MOS晶体管的漏极区的表面; 并且所述MOS晶体管的漏极区域的表面上的栅极电介质层的一部分形成所述RRAM的电阻可变存储层。在本发明中，MOS晶体管的高质量电介质层和RRAM的电阻可变存储层是通过在不增加步骤的情况下将RRAM和MOS晶体管集成在一起的原子层沉积获得的。该工艺简单，可以结合浅沟槽隔离或场氧隔离以及源电极和漏电极的离子注入或扩散，使集成方便。

8. 发明授权

US09147835B2 Tunnel transistor structure integrated with a resistance random access memory (RRAM) and a manufacturing method thereof 有权
标题翻译：与电阻随机存取存储器（RRAM）集成的隧道晶体管结构及其制造方法
公开(公告)号：US09147835B2
公开(公告)日：2015-09-29
申请号：US13663180
申请日：2012-10-29
申请人： Fudan University
发明人： Xi Lin , Pengfei Wang , Qingqing Sun , Wei Zhang
IPC分类号： H01L29/76 , H01L45/00 , H01L27/24
CPC分类号： H01L45/1206 , H01L27/2436 , H01L45/04 , H01L45/1233 , H01L45/146 , H01L45/16 , H01L45/1616
摘要： The invention relates to the technical field of semiconductor memories, in particular to a tunnel transistor structure integrated with a resistance random access memory and a manufacturing method thereof. The tunnel transistor structure in the present invention comprises a semiconductor substrate, and a tunnel transistor and a resistance random access memory formed on the semiconductor substrate, wherein the gate dielectric layer of the tunnel transistor extends to the surface of a drain region of the tunnel transistor; the part of the gate dielectric layer on the surface of the drain region of the tunnel transistor forms the resistance-variable storage layer of the resistance random access memory. In this invention, the high-quality gate dielectric layer of the tunnel transistor and the resistance-variable storage layer of the resistance random access memory are obtained by primary atomic layer deposition which integrates the resistance random access memory and tunnel transistor together without increasing steps. This process is simple and can combine the shallow trench isolation or field oxygen isolation and ion implantation or diffusion of source electrode and drain electrode to make integration convenient.
摘要翻译：本发明涉及半导体存储器的技术领域，特别涉及与电阻随机存取存储器集成的隧道晶体管结构及其制造方法。本发明的隧道晶体管结构包括半导体衬底和形成在半导体衬底上的隧道晶体管和电阻随机存取存储器，其中隧道晶体管的栅介质层延伸到隧道晶体管的漏极区的表面 ; 隧道晶体管的漏极区域的表面上的栅极电介质层的一部分形成电阻随机存取存储器的电阻变化存储层。在本发明中，隧道晶体管的高质量栅极电介质层和电阻随机存取存储器的电阻可变存储层通过主要原子层沉积获得，其将电阻随机存取存储器和隧道晶体管集成在一起而不增加步骤。该工艺简单，可以结合浅沟槽隔离或场氧隔离以及源电极和漏电极的离子注入或扩散，使集成方便。

9. 发明申请

US20140306271A1 Unltra-Shallow Junction Semiconductor Field-Effect Transistor and Method of Making 有权
标题翻译： Unltra-Shallow Junction半导体场效应晶体管及其制作方法
公开(公告)号：US20140306271A1
公开(公告)日：2014-10-16
申请号：US13704598
申请日：2012-12-12
申请人： Fudan University
发明人： Dongping Wu , Xiangbiao Zhou , Peng Xu , Wei Zhang , Shili Zhang
IPC分类号： H01L21/225 , H01L29/78 , H01L29/66
CPC分类号： H01L21/225 , H01L21/2254 , H01L29/665 , H01L29/66575 , H01L29/78
摘要： An ultra-shallow junction semiconductor field-effect transistor and its methods of making are disclosed. In the present disclosure, a mixture film is formed on a semiconductor substrate with a gate structure formed thereon using a physical vapor deposition (PVD) process, which employs a mixture of metal and semiconductor dopants as a target. The PVD process is followed by annealing, during which ultra-shallow junctions and ultra-thin metal silicide are formed. After removing the mixture film remaining on the semiconductor substrate, an ultra-shallow junction semiconductor field-effect transistor is formed. Because the mixture film comprises metal and semiconductor dopants, ultra-shallow junctions and ultra-thin metal silicide can be formed in a same annealing process. The ultra-shallow junction thus formed can be used in semiconductor field-effect transistors for the 14 nm, 11 nm, or even further technology node.
摘要翻译：公开了一种超浅结半导体场效应晶体管及其制造方法。在本公开内容中，使用以金属和半导体掺杂剂的混合物为目标的物理气相沉积（PVD）工艺在其上形成有栅极结构的半导体衬底上形成混合膜。 PVD工艺后进行退火，在此期间形成超浅结和超薄金属硅化物。在去除残留在半导体衬底上的混合物膜之后，形成超浅结半导体场效应晶体管。因为混合物膜包括金属和半导体掺杂剂，所以可以在相同的退火工艺中形成超浅结和超薄金属硅化物。如此形成的超浅结可用于14纳米，11纳米甚至更远的技术节点的半导体场效应晶体管。

10. 发明授权

US09385005B2 Semiconductor device and method of making 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US09385005B2
公开(公告)日：2016-07-05
申请号：US13704614
申请日：2012-12-14
申请人： Fudan University
发明人： Dongping Wu , Zhaoyang Pi , Na Zhao , Wei Zhang , Shi-Li Zhang
IPC分类号： H01L21/4763 , H01L21/48 , H01L21/768 , H01L29/45 , H01L23/485 , H01L23/532
CPC分类号： H01L21/486 , H01L21/76843 , H01L21/76855 , H01L21/76883 , H01L21/76889 , H01L23/485 , H01L23/53271 , H01L29/458 , H01L2924/0002 , H01L2924/00
摘要： The present disclosure is related to semiconductor technologies and discloses a semiconductor device and its method of making. In the present disclosure, a transistor's source and drain are led out by forming vias or contact holes in an insulator layer covering the transistor and at metal silicide contact regions corresponding to the source and drain, and by filling the vias with metal-semiconductor compound. Because the metal-semiconductor compound has relatively low resistivity, the resistance of the material in the vias can be minimized. Also, because the material used to fill the vias and the material forming the source/drain contact regions are both metal-semiconductor compound, contact resistance between the material filling the vias and the source/drain contact regions can be minimized. Furthermore, because the material filling the vias is metal-semiconductor compound, the conducting material in the vias and dielectric material in the insulator layer can form good interface and have good adhesion properties, and the conducting material would not cause structural damage in the dielectric material. Thus, there is no need to form a barrier layer between the insulator layer and the material filling the vias.
摘要翻译：本公开涉及半导体技术，并公开了一种半导体器件及其制造方法。在本公开内容中，通过在覆盖晶体管的绝缘体层和对应于源极和漏极的金属硅化物接触区域处形成通孔或接触孔，并且通过用金属半导体化合物填充通孔来引出晶体管的源极和漏极。因为金属 - 半导体化合物具有相对较低的电阻率，所以可以使过孔中的材料的电阻最小化。此外，由于用于填充通孔的材料和形成源极/漏极接触区域的材料都是金属 - 半导体化合物，所以填充通孔的材料与源极/漏极接触区域之间的接触电阻可以最小化。此外，由于填充过孔的材料是金属 - 半导体化合物，所以绝缘体层中的通孔和电介质材料中的导电材料可以形成良好的界面并且具有良好的粘合性能，并且导电材料不会在介电材料中引起结构损坏。因此，不需要在绝缘体层和填充通孔的材料之间形成阻挡层。

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