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1. 发明申请

US20050276332A1 Method of communicating data within a coder 审中-公开
标题翻译：在编码器内传送数据的方法
公开(公告)号：US20050276332A1
公开(公告)日：2005-12-15
申请号：US10523387
申请日：2003-06-16
申请人： Erik Van Der Tol , Gerben Hekstra , Evert-Jan Pol , Josephus Theodorus Van Eijndhoven
发明人： Erik Van Der Tol , Gerben Hekstra , Evert-Jan Pol , Josephus Theodorus Van Eijndhoven
IPC分类号： H03M7/30 , H04N7/26 , H04N7/30 , H04N7/50 , H04N7/12
CPC分类号： H04N19/423 , H04N19/60 , H04N19/61
摘要： Transform based coders are frequently used in digital signal processing. The present invention relates to a method of communicating at least one block of data from a first functional element (3; 4; 7; 12; 14) within a transform based coder (1) or decoder (10) to a second functional element (4; 5; 7; 8; 14; 15) within the coder or decoder, where the block of data comprises a row-column structure of data coefficients. A significant communication workload occurs between individual elements of the coders and decoders. The present invention seeks to reduce this work-load by making an effort to communicate only non-zero coefficients within a cartesian bounding box of a block between various functional units in a decoding or encoding scheme by reducing the size of the at least one block of data to produce a reduced size data block by elimination (31) of one or more rows and/or columns of substantially zero valued coefficients, and communicating (32) the reduced size data block from the first functional element to the second functional element.
摘要翻译：基于变换的编码器经常用于数字信号处理。本发明涉及一种将至少一个数据块从基于变换的编码器（1）或解码器（10）内的第一功能元件（3; 4; 7; 12; 14）传送到第二功能元件 4; 5; 7; 8; 14; 15），其中数据块包括数据系数的行列结构。在编码器和解码器的各个元件之间发生重大的通信工作。本发明寻求通过在解码或编码方案中通过减小至少一个块的大小来努力仅在各种功能单元之间的块的笛卡尔边界框内通信的非零系数，来减少该工作负载数据，以通过消除（31）一个或多个基本上零值系数的行和/或列来产生减小尺寸的数据块，并将缩小尺寸的数据块从第一功能元件传送到第二功能元件。

2. 发明申请

US20050081200A1 Data processing system having multiple processors, a task scheduler for a data processing system having multiple processors and a corresponding method for task scheduling 审中-公开
标题翻译：具有多个处理器的数据处理系统，具有多个处理器的数据处理系统的任务调度器和用于任务调度的相应方法
公开(公告)号：US20050081200A1
公开(公告)日：2005-04-14
申请号：US10498298
申请日：2002-12-05
申请人： Martijn Rutten , Josephus Theodorus Van Eijndhoven , Evert-Jan Pol
发明人： Martijn Rutten , Josephus Theodorus Van Eijndhoven , Evert-Jan Pol
IPC分类号： G06F9/46 , G06F9/48 , G06F9/50
CPC分类号： G06F9/4881 , G06F2209/485
摘要： The invention is based on the idea to provide distributed task scheduling in a data processing system having multiple processors. Therefore, a data processing system comprising a first and at least one second processor for processing a stream of data objects, wherein said first processor passes data objects from a stream of data objects to the second processor, and a communication network and a memory is provided. Said second processors are multi-tasking processors, capable of interleaved processing of a first and second task, wherein said first and second tasks process a first and second stream of data objects, respectively. Said data processing system further comprises a task scheduling means for each of said second processors, wherein said task scheduling means is operatively arranged between said second processor and said communication network, and controls the task scheduling of said second processor.
摘要翻译：本发明基于在具有多个处理器的数据处理系统中提供分布式任务调度的思想。因此，数据处理系统包括用于处理数据对象流的第一和至少一个第二处理器，其中所述第一处理器将数据对象从数据对象流传递到第二处理器，并且提供通信网络和存储器。所述第二处理器是能够进行第一和第二任务的交错处理的多任务处理器，其中所述第一和第二任务分别处理第一和第二数据对象流。所述数据处理系统还包括用于每个所述第二处理器的任务调度装置，其中所述任务调度装置可操作地布置在所述第二处理器和所述通信网络之间，并且控制所述第二处理器的任务调度。

3. 发明申请

US20060290776A1 Data processing system having a plurality of processing elements, a method of controlling a data processing system having a plurality of processing elements 审中-公开
标题翻译：具有多个处理元件的数据处理系统，具有多个处理元件的数据处理系统的控制方法
公开(公告)号：US20060290776A1
公开(公告)日：2006-12-28
申请号：US10546316
申请日：2004-02-18
申请人： Martijn Rutten , Josephus Theodorus Van Eijndhoven , Evert-Jan Pol
发明人： Martijn Rutten , Josephus Theodorus Van Eijndhoven , Evert-Jan Pol
IPC分类号： H04N7/14
CPC分类号： G06F9/52 , G06F9/4494
摘要： The invention relates to task management in a data processing system, having a plurality of processing elements (CPU, ProcA, ProcB, ProcC). Therefore a data processing system is provided, comprising at least a first processing element (CPU, ProcA, ProcB, ProcC) and a second processing element (CPU, ProcA, ProcB, ProcC) for processing a stream of data objects (DS_Q, DS R, DS S, DST), the first processing element being arranged to pass data objects from the stream of data objects to the second processing element The first and the second processing element are arranged for parallel execution of an application comprising a set of tasks (TP, TA, TB1, TB2, TC), and the first and the second processing element are arranged to be responsive to the receipt of a unique identifier. In order to ensure integrity of data during reconfiguration of the application, the unique identifier is inserted into data stream and passed from one processing element to the other. Application reconfiguration is performed when the corresponding processing element receives the unique identifier, and as a result global application control is allowed at a unique location in the data space.
摘要翻译：本发明涉及具有多个处理元件（CPU，ProcA，ProcB，ProcC）的数据处理系统中的任务管理。因此，提供了一种数据处理系统，其至少包括用于处理数据对象流（DS_Q，DSR）的至少第一处理元件（CPU，ProcA，ProcB，ProcC）和第二处理元件（CPU，ProcA，ProcB，ProcC），DSS，DST），第一处理元件被布置为将数据对象从数据对象流传递到第二处理元件。第一和第二处理元件被布置为用于并行执行包括一组任务（TP ，TA，TB1，TB2，TC），并且第一和第二处理元件被布置成响应于唯一标识符的接收。为了确保在重新配置应用程序期间数据的完整性，将唯一标识符插入到数据流中，并从一个处理元件传递到另一个处理元件。当对应的处理单元接收到唯一标识符时执行应用重新配置，从而在数据空间中的唯一位置允许全局应用控制。

4. 发明申请

US20070168615A1 Data processing system with cache optimised for processing dataflow applications 审中-公开
标题翻译：数据处理系统具有针对处理数据流应用程序优化的缓存
公开(公告)号：US20070168615A1
公开(公告)日：2007-07-19
申请号：US10547595
申请日：2004-02-25
申请人： Josephus Theodorus Van Eijndhoven , Martijn Rutten , Evert-Jan Pol
发明人： Josephus Theodorus Van Eijndhoven , Martijn Rutten , Evert-Jan Pol
IPC分类号： G06F12/00
CPC分类号： G06F12/084
摘要： Non-overlapping cache locations are reserved for each data stream. Therefore, stream information, which is unique to each stream, is used to index the cache memory. Here, this stream information is represented by the stream identification. In particular, a data processing system optimised for processing dataflow applications with tasks and data streams, where different streams compete for shared cache resources is provided. An unambiguous stream identification is associated to each of said data stream. Said data processing system comprises at least one processor (12) for processing streaming data, at least one cache memory (200) having a plurality of cache blocks, wherein one of said cache memories (200) is associated to each of said processors (12), and at least one cache controller (300) for controlling said cache memory (200), wherein one of said cache controllers (300) is associated to each of said cache memories (200). Said cache controller (300) comprises selecting means (350) for selecting locations for storing elements of a data stream in said cache memory (200) in accordance to said stream identification (stream_id).
摘要翻译：为每个数据流保留非重叠缓存位置。因此，每个流唯一的流信息用于对高速缓冲存储器进行索引。这里，流信息由流标识表示。特别地，提供了优化用于处理具有任务和数据流的数据流应用的数据处理系统，其中不同流竞争共享高速缓存资源。明确的流识别与每个所述数据流相关联。所述数据处理系统包括用于处理流数据的至少一个处理器（12），具有多个高速缓存块的至少一个高速缓冲存储器（200），其中所述高速缓冲存储器（200）中的一个与每个所述处理器）和用于控制所述高速缓冲存储器（200）的至少一个高速缓存控制器（300），其中所述高速缓存控制器（300）中的一个与所述高速缓冲存储器（200）中的每一个相关联。所述缓存控制器（300）包括选择装置（350），用于根据所述流标识（stream_id）选择用于存储所述高速缓冲存储器（200）中的数据流元素的位置。

5. 发明申请

US20060190688A1 Data processing system with prefetching means 有权
标题翻译：具有预取方式的数据处理系统
公开(公告)号：US20060190688A1
公开(公告)日：2006-08-24
申请号：US10547594
申请日：2004-02-25
申请人： Josephus Theodorus Van Eijndhoven , Martijn Rutten , Evert-Jan Pol
发明人： Josephus Theodorus Van Eijndhoven , Martijn Rutten , Evert-Jan Pol
IPC分类号： G06F13/28
CPC分类号： G06F12/0862
摘要： The dismissing of cached data that is not expected to be further used is predicted instead of predicting future I/O operations and then data is fetched from the main memory to replace the dismissed data in the cache. Thus, firstly a location in a cache memory containing data, which is expected not to be further used, is identified, followed by performing a prefetch operation in order to request new data to refill the above location in the cache memory. Therefore, a data processing system comprises at least one processor (12) for processing streaming data, at least one cache memory (200) having a plurality of cache blocks (210), wherein one of said cache memories (200) is associated to each of said processors (12), and at least one cache controller (300) for prefetching data into said cache memory (200), wherein one of said cache controllers (300) is associated to each of said cache memories (200). Said cache controller (300) comprises determining means (350) for identifying at least one location in said cache memory (200) containing first data, which is predicted to be dismissible without penalty and prefetch means (320) for issuing a prefetch operation replacing said first data at said location with second data, which fit said location.
摘要翻译：预测不预期会被进一步使用的缓存数据的解除，而不是预测未来的I / O操作，然后从主存储器中取出数据以替换高速缓存中的被解除的数据。因此，首先识别包含期望不被进一步使用的数据的高速缓冲存储器中的位置，然后执行预取操作以便请求新数据以将高速缓冲存储器中的上述位置重新填充。因此，数据处理系统包括用于处理流数据的至少一个处理器（12），具有多个高速缓存块（210）的至少一个高速缓冲存储器（200），其中所述高速缓冲存储器（200）中的一个与每个的所述处理器（12）以及用于将数据预取到所述高速缓冲存储器（200）中的至少一个高速缓存控制器（300），其中所述高速缓存控制器（300）中的一个与所述高速缓冲存储器（200）中的每一个相关联。所述高速缓存控制器（300）包括用于识别所述高速缓冲存储器（200）中的至少一个位置的确定装置（350），其包含被预测为无需罚款的第一数据，以及用于发出预取操作的预取装置（320）所述位置处的第一数据具有适合所述位置的第二数据。

6. 发明申请

US20070088983A1 Integrated circuit comprising a measurement unit for measuring utlization 审中-公开
标题翻译：集成电路，包括用于测量ut值的测量单元
公开(公告)号：US20070088983A1
公开(公告)日：2007-04-19
申请号：US10577536
申请日：2004-10-20
申请人： Abraham Riemens , Josephus Theodorus Van Eijndhoven
发明人： Abraham Riemens , Josephus Theodorus Van Eijndhoven
IPC分类号： G06F11/00
CPC分类号： G06F11/349
摘要： The invention provides an integrated circuit comprising a data processing system which performs satisfactorily after integration of the individual building blocks, such as main processors and coprocessors, into the data processing system. This is achieved by measuring the utilization of the communication structure established between the individual building blocks. A measurement unit measures properties of the communication load by observing the communication traffic on connections between processing units and a communication resource, or on connections within the communication resource. The measurement unit performs statistical operations on the observed properties and produces measurement results. The measurement results can be retrieved by measurement software and can be used to modify the data processing system, for example by debugging or by adaptive control.
摘要翻译：本发明提供了一种集成电路，其包括在将诸如主处理器和协处理器的各个构建块集成到数据处理系统中之后令人满意地执行的数据处理系统。这是通过测量在各个构建块之间建立的通信结构的利用来实现的。测量单元通过观察处理单元和通信资源之间的连接上的通信流量，或通信资源内的连接来测量通信负载的属性。测量单元对观察到的属性执行统计运算，并产生测量结果。测量结果可以通过测量软件进行检索，可以通过调试或通过自适应控制来修改数据处理系统。

7. 发明申请

US20060053254A1 Data processing system and method for operating the same 有权
标题翻译：数据处理系统及其操作方法
公开(公告)号：US20060053254A1
公开(公告)日：2006-03-09
申请号：US10530143
申请日：2003-10-01
申请人： Josephus Theodorus Van Eijndhoven
发明人： Josephus Theodorus Van Eijndhoven
IPC分类号： G06F12/00
CPC分类号： G06F12/0811 , G06F12/0897
摘要： A data processing system according to the invention comprises a processor (P) and a memory hierarchy. The highest ranked level therein is a cache coupled to the processor. The memory hierarchy comprises a higher ranked cache (C1) having a cache controller (CC1) operating according to a write allocate scheme, and a lower ranked cache (C2) is coupled to the higher ranked cache (C1) having a cache controller (CC2). The size of the higher ranked cache is smaller than the size of the lower ranked cache. Both caches (C1, C2) administrate auxiliary information (V1, V2) indicating whether data (D1, D2) present therein is valid. The linesize of the lowerranked cache (C2) is an integer multiple of the linesize of the higher ranked cache (C1). The auxiliary information (V1) in the higher ranked cache (C1) concerns data elements (D1) at a finer granularity than that in the lower ranked cache (C2). The higher ranked cache (C1) is arranged for transmitting a writemask (WM) to the lower ranked cache (C2) in conjunction with a line of data (DL) for indicating which data in the lower ranked cache (C2) is to be overwritten at the finer granularity. Fetching a line from the next lower ranked level (M) is suppressed if the writemask (WM) indicates that the line (DL) provided by the higher ranked cache (C1) is entirely valid in which case, the controller (CC2) of the lower ranked cache allocates the cache line in the lower ranked cache (C2) without fetching it.
摘要翻译：根据本发明的数据处理系统包括处理器（P）和存储器层级。其中最高排名的级别是耦合到处理器的高速缓存。存储器层级包括具有根据写分配方案操作的高速缓存控制器（CC 1）的较高等级的高速缓存（C 1），并且较低等级的高速缓存（C 2）耦合到具有缓存控制器（CC 2）。较高排名的缓存的大小小于较低排名的高速缓存的大小。两个高速缓存（C 1，C 2）管理表示其中存在的数据（D 1，D 2）是否有效的辅助信息（V 1，V 2）。低排高速缓存（C 2）的线性化是较高等级的高速缓存（C 1）的线性化的整数倍。较高等级的高速缓存（C 1）中的辅助信息（V 1）以比较低等级的高速缓存（C 2）更细的粒度关系数据元素（D1）。排列较高的高速缓存（C 1）用于结合用于指示较低等级的高速缓冲存储器（C 2）中的哪个数据（DL）的数据行（DL）将写入掩码（WM）发送到较低等级的高速缓存（C 2）以更细的粒度被覆盖。如果写入掩码（WM）指示由较高等级的高速缓存（C 1）提供的行（DL）完全有效，则控制器（CC 2）被禁止，从而从下一个较低等级（M）获取行被抑制较低等级的高速缓存（C 2）中的高速缓存行分配高速缓存行，而不读取它。

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