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1. 发明申请

US20120185703A1 Coordinating Performance Parameters in Multiple Circuits 有权
标题翻译：多电路协调性能参数
公开(公告)号：US20120185703A1
公开(公告)日：2012-07-19
申请号：US13006967
申请日：2011-01-14
申请人： Erik P. Machnicki , Timothy J. Millet , Josh P. de Cesare
发明人： Erik P. Machnicki , Timothy J. Millet , Josh P. de Cesare
IPC分类号： G06F1/00
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/3287 , G06F1/3296 , Y02D10/126 , Y02D10/171 , Y02D10/172
摘要： Systems and methods for coordinating performance parameters in multiple domains are described. In an embodiment, a method includes receiving a request to change a state of an electronic circuit, where the circuit includes a first domain and a second domain, causing a first parameter of a first circuit serving the first domain to be modified to a first modified parameter based on the request, and causing a second parameter of a second circuit serving the second domain to be modified to a second modified parameter based on the request. In some cases, a parameter may include a clock frequency. In other cases, a parameter may include a voltage. In some embodiments, a system may be implemented as a logic circuit and/or as a system-on-a-chip (SoC). Devices suitable for using these systems include, for example, desktop and laptop computers, tablets, network appliances, mobile phones, personal digital assistants, e-book readers, televisions, and game consoles.
摘要翻译：描述用于协调多个域中的性能参数的系统和方法。在一个实施例中，一种方法包括接收改变电子电路的状态的请求，其中电路包括第一域和第二域，使得服务于第一域的第一电路的第一参数被修改为第一修改参数，并且基于该请求，使服务于第二域的第二电路的第二参数被修改为第二修改参数。在一些情况下，参数可以包括时钟频率。在其他情况下，参数可以包括电压。在一些实施例中，系统可以被实现为逻辑电路和/或作为片上系统（SoC）。适用于这些系统的设备包括例如台式和膝上型计算机，平板电脑，网络设备，移动电话，个人数字助理，电子书阅读器，电视机和游戏机。

2. 发明授权

US08468373B2 Modifying performance parameters in multiple circuits according to a performance state table upon receiving a request to change a performance state 有权
标题翻译：在接收到改变性能状态的请求时，根据性能状态表来修改多个电路中的性能参数
公开(公告)号：US08468373B2
公开(公告)日：2013-06-18
申请号：US13006967
申请日：2011-01-14
申请人： Erik P. Machnicki , Timothy J. Millet , Josh P. de Cesare
发明人： Erik P. Machnicki , Timothy J. Millet , Josh P. de Cesare
IPC分类号： G06F1/00
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/3287 , G06F1/3296 , Y02D10/126 , Y02D10/171 , Y02D10/172
摘要： Systems and methods for coordinating performance parameters in multiple domains are described. In an embodiment, a method includes receiving a request to change a state of an electronic circuit, where the circuit includes a first domain and a second domain, causing a first parameter of a first circuit serving the first domain to be modified to a first modified parameter based on the request, and causing a second parameter of a second circuit serving the second domain to be modified to a second modified parameter based on the request. In some cases, a parameter may include a clock frequency. In other cases, a parameter may include a voltage. In some embodiments, a system may be implemented as a logic circuit and/or as a system-on-a-chip (SoC). Devices suitable for using these systems include, for example, desktop and laptop computers, tablets, network appliances, mobile phones, personal digital assistants, e-book readers, televisions, and game consoles.
摘要翻译：描述用于协调多个域中的性能参数的系统和方法。在一个实施例中，一种方法包括接收改变电子电路的状态的请求，其中电路包括第一域和第二域，使得服务于第一域的第一电路的第一参数被修改为第一修改参数，并且基于该请求，使服务于第二域的第二电路的第二参数被修改为第二修改参数。在一些情况下，参数可以包括时钟频率。在其他情况下，参数可以包括电压。在一些实施例中，系统可以被实现为逻辑电路和/或作为片上系统（SoC）。适用于这些系统的设备包括例如台式和膝上型计算机，平板电脑，网络设备，移动电话，个人数字助理，电子书阅读器，电视机和游戏机。

3. 发明授权

US08443216B2 Hardware automatic performance state transitions in system on processor sleep and wake events 有权
公开(公告)号：US08443216B2
公开(公告)日：2013-05-14
申请号：US13590217
申请日：2012-08-21
申请人： Josh P. de Cesare , Jung Wook Cho , Toshi Takayanagi , Timothy J. Millet
发明人： Josh P. de Cesare , Jung Wook Cho , Toshi Takayanagi , Timothy J. Millet
IPC分类号： G06F1/00 , G06F1/26 , G06F3/038 , G06F3/00 , G09G3/18 , G11C5/14 , H04M1/00
CPC分类号： G06F1/26 , G06F1/3203 , G06F1/3234 , G06F1/3237 , G06F1/3287 , Y02D10/126 , Y02D10/128 , Y02D10/17 , Y02D10/171 , Y02D50/20
摘要： In an embodiment, a power management unit (PMU) may automatically transition (in hardware) the performance states of one or more performance domains in a system. The target performance states to which the performance domains are to transition may be programmable in the PMU by software, and software may signal the PMU that a processor in the system is to enter the sleep state. The PMU may control the transition of the performance domains to the target performance states, and may cause the processor to enter the sleep state. In an embodiment, the PMU may be programmable with a second set of target performance states to which the performance domains are to transition when the processor exits the sleep state. The PMU may control the transition of the performance domains to the second targeted performance states and cause the processor to exit the sleep state.

4. 发明申请

US20120317427A1 Hardware Automatic Performance State Transitions in System on Processor Sleep and Wake Events 有权
标题翻译：处理器睡眠和唤醒事件的硬件自动性能状态转换系统
公开(公告)号：US20120317427A1
公开(公告)日：2012-12-13
申请号：US13590217
申请日：2012-08-21
申请人： Josh P. de Cesare , Jung Wook Cho , Toshi Takayanagi , Timothy J. Millet
发明人： Josh P. de Cesare , Jung Wook Cho , Toshi Takayanagi , Timothy J. Millet
IPC分类号： G06F1/00 , G06F1/26
CPC分类号： G06F1/26 , G06F1/3203 , G06F1/3234 , G06F1/3237 , G06F1/3287 , Y02D10/126 , Y02D10/128 , Y02D10/17 , Y02D10/171 , Y02D50/20
摘要： In an embodiment, a power management unit (PMU) may automatically transition (in hardware) the performance states of one or more performance domains in a system. The target performance states to which the performance domains are to transition may be programmable in the PMU by software, and software may signal the PMU that a processor in the system is to enter the sleep state. The PMU may control the transition of the performance domains to the target performance states, and may cause the processor to enter the sleep state. In an embodiment, the PMU may be programmable with a second set of target performance states to which the performance domains are to transition when the processor exits the sleep state. The PMU may control the transition of the performance domains to the second targeted performance states and cause the processor to exit the sleep state.
摘要翻译：在一个实施例中，功率管理单元（PMU）可以自动地（在硬件中）转换系统中的一个或多个性能域的性能状态。性能域要转换到的目标性能状态可以通过软件在PMU中编程，并且软件可以向PMU发信号通知系统中的处理器进入睡眠状态。 PMU可以控制性能域到目标性能状态的转换，并且可能导致处理器进入睡眠状态。在一个实施例中，PMU可以是可编程的，当处理器退出睡眠状态时，性能域将转换到第二组目标性能状态。 PMU可以控制性能域到第二目标性能状态的转换，并使处理器退出睡眠状态。

5. 发明授权

US09081517B2 Hardware-based automatic clock gating 有权
标题翻译：基于硬件的自动时钟门控
公开(公告)号：US09081517B2
公开(公告)日：2015-07-14
申请号：US13223282
申请日：2011-08-31
申请人： Kleanthes Koniaris , Josh P. de Cesare , Timothy J. Millet , Jung Wook Cho , Erik Machnicki
发明人： Kleanthes Koniaris , Josh P. de Cesare , Timothy J. Millet , Jung Wook Cho , Erik Machnicki
IPC分类号： G06F1/32 , G06F1/10 , G06F1/24
CPC分类号： G06F1/10 , G06F1/24 , G06F1/3237 , Y02D10/128
摘要： A system and method for automatically updating with hardware clock tree settings on a system-on-a-chip (SOC). A SOC includes a hardware clock control unit (HCCU) coupled to a software interface and a clock tree. The SOC also includes multiple integrated circuit (IC) devices, wherein each IC device receives one or more associated core clocks provided by one or more phase lock loops (PLLs) via the clock tree. The HCCU receives a software-initiated request specifying a given IC device is to be enabled. The HCCU identifies one or more core clocks used by the given IC device. For each one of the identified core clocks, the HCCU configures associated circuitry within the clock tree to generate an identified core clock. The HCCU may also traverse the clock tree and disable clock generating gates found not to drive any other enabled gates or IC devices.
摘要翻译：一种使用片上系统（SOC）上的硬件时钟树设置自动更新的系统和方法。 SOC包括耦合到软件接口和时钟树的硬件时钟控制单元（HCCU）。 SOC还包括多个集成电路（IC）器件，其中每个IC器件经由时钟树接收由一个或多个锁相环（PLL）提供的一个或多个相关核心时钟。 HCCU接收软件发起的请求，指定要启用给定的IC设备。 HCCU识别给定IC器件使用的一个或多个核心时钟。对于每个识别的核心时钟，HCCU配置时钟树内的相关电路以产生识别的核心时钟。 HCCU还可以遍历时钟树，并禁用发现不驱动任何其他启用的门或IC设备的时钟生成门。

6. 发明授权

US08271812B2 Hardware automatic performance state transitions in system on processor sleep and wake events 有权
标题翻译：系统中处理器睡眠和唤醒事件的硬件自动性能状态转换
公开(公告)号：US08271812B2
公开(公告)日：2012-09-18
申请号：US12756006
申请日：2010-04-07
申请人： Josh P. de Cesare , Jung Wook Cho , Toshi Takayanagi , Timothy J. Millet
发明人： Josh P. de Cesare , Jung Wook Cho , Toshi Takayanagi , Timothy J. Millet
IPC分类号： G06F1/00 , G06F1/26 , G06F3/038 , G06F3/00 , G09G3/18 , G11C5/14 , H04M1/00
CPC分类号： G06F1/26 , G06F1/3203 , G06F1/3234 , G06F1/3237 , G06F1/3287 , Y02D10/126 , Y02D10/128 , Y02D10/17 , Y02D10/171 , Y02D50/20
摘要： In an embodiment, a power management unit (PMU) may automatically transition (in hardware) the performance states of one or more performance domains in a system. The target performance states to which the performance domains are to transition may be programmable in the PMU by software, and software may signal the PMU that a processor in the system is to enter the sleep state. The PMU may control the transition of the performance domains to the target performance states, and may cause the processor to enter the sleep state. In an embodiment, the PMU may be programmable with a second set of target performance states to which the performance domains are to transition when the processor exits the sleep state. The PMU may control the transition of the performance domains to the second targeted performance states and cause the processor to exit the sleep state.
摘要翻译：在一个实施例中，功率管理单元（PMU）可以自动地（在硬件中）转换系统中的一个或多个性能域的性能状态。性能域要转换到的目标性能状态可以通过软件在PMU中编程，并且软件可以向PMU发信号通知系统中的处理器进入睡眠状态。 PMU可以控制性能域到目标性能状态的转换，并且可能导致处理器进入睡眠状态。在一个实施例中，PMU可以是可编程的，当处理器退出睡眠状态时，性能域将转换到第二组目标性能状态。 PMU可以控制性能域到第二目标性能状态的转换，并使处理器退出睡眠状态。

7. 发明申请

US20110252251A1 Hardware Automatic Performance State Transitions in System on Processor Sleep and Wake Events 有权
标题翻译：处理器睡眠和唤醒事件的硬件自动性能状态转换系统
公开(公告)号：US20110252251A1
公开(公告)日：2011-10-13
申请号：US12756006
申请日：2010-04-07
申请人： Josh P. de Cesare , Jung Wook Cho , Toshi Takayanagi , Timothy J. Millet
发明人： Josh P. de Cesare , Jung Wook Cho , Toshi Takayanagi , Timothy J. Millet
IPC分类号： G06F1/32 , G06F1/00
CPC分类号： G06F1/26 , G06F1/3203 , G06F1/3234 , G06F1/3237 , G06F1/3287 , Y02D10/126 , Y02D10/128 , Y02D10/17 , Y02D10/171 , Y02D50/20
摘要： In an embodiment, a power management unit (PMU) may automatically transition (in hardware) the performance states of one or more performance domains in a system. The target performance states to which the performance domains are to transition may be programmable in the PMU by software, and software may signal the PMU that a processor in the system is to enter the sleep state. The PMU may control the transition of the performance domains to the target performance states, and may cause the processor to enter the sleep state. In an embodiment, the PMU may be programmable with a second set of target performance states to which the performance domains are to transition when the processor exits the sleep state. The PMU may control the transition of the performance domains to the second targeted performance states and cause the processor to exit the sleep state.
摘要翻译：在一个实施例中，功率管理单元（PMU）可以自动地（在硬件中）转换系统中的一个或多个性能域的性能状态。性能域要转换到的目标性能状态可以通过软件在PMU中编程，并且软件可以向PMU发信号通知系统中的处理器进入睡眠状态。 PMU可以控制性能域到目标性能状态的转换，并且可能导致处理器进入睡眠状态。在一个实施例中，PMU可以是可编程的，当处理器退出睡眠状态时，性能域将转换到第二组目标性能状态。 PMU可以控制性能域到第二目标性能状态的转换，并使处理器退出睡眠状态。

8. 发明申请

US20120144224A1 Adjusting a Device Clock Source to Reduce Wireless Communication Interference 有权
标题翻译：调整设备时钟源以减少无线通信干扰
公开(公告)号：US20120144224A1
公开(公告)日：2012-06-07
申请号：US12960708
申请日：2010-12-06
申请人： Erik P. Machnicki , Timothy J. Millet , Stephan Vincent Schell
发明人： Erik P. Machnicki , Timothy J. Millet , Stephan Vincent Schell
IPC分类号： G06F1/08
CPC分类号： G06F1/08 , H04B15/06
摘要： Adjusting a clock source of a device clock to reduce wireless communication (e.g., radio frequency (RF)) interference within a device. The device clock may be derived from an input clock to a serial interface, e.g., coupled to a display, and may be initially driven by a first clock. Later, it may be determined that the serial interface clock is or will interfere with wireless communication. Accordingly, temporary clock signals may be provided to the device clock while the first clock is modified. Once modified, the modified clock signals may be provided to the device clock to reduce wireless communication interference.
摘要翻译：调整设备时钟的时钟源以减少设备内的无线通信（例如射频（RF））干扰。设备时钟可以从例如耦合到显示器的串行接口的输入时钟导出，并且可以最初由第一时钟驱动。之后，可以确定串行接口时钟是或将会干扰无线通信。因此，在修改第一时钟的同时，可以将临时时钟信号提供给设备时钟。一旦被修改，修改的时钟信号可以被提供给设备时钟以减少无线通信干扰。

9. 发明申请

US20120084589A1 Hardware Dynamic Cache Power Management 有权
标题翻译：硬件动态高速缓存电源管理
公开(公告)号：US20120084589A1
公开(公告)日：2012-04-05
申请号：US12894516
申请日：2010-09-30
申请人： Timothy J. Millet , Erik P. Machnicki , Deniz Balkan , Vijay Gupta
发明人： Timothy J. Millet , Erik P. Machnicki , Deniz Balkan , Vijay Gupta
IPC分类号： G06F1/32
CPC分类号： G06F1/3203 , G06F1/3275 , G06F1/3287 , G06F12/0802 , G06F2212/1028 , Y02D10/13 , Y02D10/14 , Y02D10/171 , Y02D50/20
摘要： In an embodiment, a control circuit is configured to transmit operations to a circuit block that is being powered up after being powered down, to reinitialize the circuit block for operation. The operations may be stored in a memory (e.g. a set of registers) to which the control circuit is coupled. In an embodiment, the control circuit may also be configured to transmit other operations from the memory to the circuit block prior to the circuit block being powered down. Accordingly, the circuit block may be powered up or powered down even during times that the processors in the system are powered down (and thus software is not executable at the time), without waking the processors for the power up/power down event. In an embodiment, the circuit block may be a cache coupled to the one or more processors.
摘要翻译：在一个实施例中，控制电路被配置为向断电后正在上电的电路块传送操作，以重新初始化电路块以进行操作。操作可以存储在控制电路耦合到的存储器（例如一组寄存器）中。在一个实施例中，控制电路还可以被配置为在电路块断电之前将其他操作从存储器传送到电路块。因此，即使在系统中的处理器断电（并且因此软件不可执行的时候），即使在唤醒处理器以进行上电/断电事件的时间内，电路块也可以上电或掉电。在一个实施例中，电路块可以是耦合到一个或多个处理器的高速缓存器。

10. 发明授权

US08806232B2 Systems and method for hardware dynamic cache power management via bridge and power manager 有权
标题翻译：通过桥和电源管理器进行硬件动态高速缓存电源管理的系统和方法
公开(公告)号：US08806232B2
公开(公告)日：2014-08-12
申请号：US12894516
申请日：2010-09-30
申请人： Timothy J. Millet , Erik P. Machnicki , Deniz Balkan , Vijay Gupta
发明人： Timothy J. Millet , Erik P. Machnicki , Deniz Balkan , Vijay Gupta
IPC分类号： G06F1/00 , G06F1/26 , G06F1/32 , G06F13/28 , G06F12/08
CPC分类号： G06F1/3203 , G06F1/3275 , G06F1/3287 , G06F12/0802 , G06F2212/1028 , Y02D10/13 , Y02D10/14 , Y02D10/171 , Y02D50/20
摘要： In an embodiment, a control circuit is configured to transmit operations to a circuit block that is being powered up after being powered down, to reinitialize the circuit block for operation. The operations may be stored in a memory (e.g. a set of registers) to which the control circuit is coupled. In an embodiment, the control circuit may also be configured to transmit other operations from the memory to the circuit block prior to the circuit block being powered down. Accordingly, the circuit block may be powered up or powered down even during times that the processors in the system are powered down (and thus software is not executable at the time), without waking the processors for the power up/power down event. In an embodiment, the circuit block may be a cache coupled to the one or more processors.
摘要翻译：在一个实施例中，控制电路被配置为向断电后正在上电的电路块传送操作，以重新初始化电路块以进行操作。操作可以存储在控制电路耦合到的存储器（例如一组寄存器）中。在一个实施例中，控制电路还可以被配置为在电路块断电之前将其他操作从存储器传送到电路块。因此，即使在系统中的处理器断电（并且因此软件不可执行的时候），即使在唤醒处理器以进行上电/断电事件的时间内，电路块也可以上电或掉电。在一个实施例中，电路块可以是耦合到一个或多个处理器的高速缓存器。

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