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1. 发明授权

US08880782B2 Memory array including multi-state memory devices 有权
标题翻译：存储阵列包括多状态存储器件
公开(公告)号：US08880782B2
公开(公告)日：2014-11-04
申请号：US13277837
申请日：2011-10-20
申请人： Erik Ordentlich , Ron M. Roth , Gadiel Seroussi
发明人： Erik Ordentlich , Ron M. Roth , Gadiel Seroussi
IPC分类号： G06F12/00 , G11C13/00 , G11C11/56 , G11C7/10 , G11C16/00
CPC分类号： G11C16/00 , G11C7/1006 , G11C11/56 , G11C11/5628 , G11C11/5642 , G11C11/5685 , G11C13/004 , G11C13/0069
摘要： A data storage system including a memory array including a plurality of memory devices programmable in greater than two states. A memory control module may control operations of the memory array, and an encoder module may encode input data for storing to the memory array. The memory array may be an m×n memory array, and the memory control module may control operations of storing data to and retrieving data from the memory array.
摘要翻译：一种数据存储系统，包括存储器阵列，所述存储器阵列包括可在大于两个状态下编程的多个存储器件。存储器控制模块可以控制存储器阵列的操作，并且编码器模块可以编码用于存储到存储器阵列的输入数据。存储器阵列可以是m×n个存储器阵列，并且存储器控制模块可以控制将数据存储到存储器阵列中并从存储器阵列检索数据的操作。

2. 发明申请

US20130262759A1 Minimized Half-Select Current in Multi-State Memories 有权
标题翻译：在多状态记忆中最小化半选择电流
公开(公告)号：US20130262759A1
公开(公告)日：2013-10-03
申请号：US13438438
申请日：2012-04-03
申请人： Erik Ordentlich , Ron M. Roth , Gadiel Seroussi
发明人： Erik Ordentlich , Ron M. Roth , Gadiel Seroussi
IPC分类号： G06F12/08
CPC分类号： G11C16/10 , G06F11/1008 , G11C7/1006 , G11C11/56 , G11C11/5678 , G11C11/5685 , G11C13/0004 , G11C13/0007
摘要： A multi-state memory system with encoding that minimizes half-select currents. The system includes an array of row and column conductors with a plurality of storage cells each capable of being placed into any of three or more physical states. An encoder is connected to receive data bits for storage and to apply activation signals to the row and column conductors to write information to the storage cells. The encoder is programmed to encode the data bits into entries in an array having one row corresponding with each row conductor and one column corresponding with each column conductor; select entries in the array according to half-select currents of the storage cells; apply a predetermined one-dimensional mapping that increases the value of at most one entry in the array to obtain a mapped array; and write entries of the mapped array into the storage cells.
摘要翻译：具有最小化半选择电流的编码的多状态存储器系统。该系统包括具有多个存储单元的行和列导体的阵列，每个存储单元能够被置于三个或更多个物理状态中的任何一个中。连接编码器以接收用于存储的数据位，并将激活信号施加到行和列导体以将信息写入存储单元。编码器被编程为将数据位编码为具有与每行导体相对应的一行的阵列中的条目和与每个列导体相对应的一列; 根据存储单元的半选择电流选择阵列中的条目; 应用增加阵列中至多一个条目的值以获得映射数组的预定一维映射; 并将映射的阵列的条目写入存储单元。

3. 发明申请

US20130103888A1 MEMORY ARRAY INCLUDING MULTI-STATE MEMORY DEVICES 有权
标题翻译：内存阵列，包括多状态存储器件
公开(公告)号：US20130103888A1
公开(公告)日：2013-04-25
申请号：US13277837
申请日：2011-10-20
申请人： Erik Ordentlich , Ron M. Roth , Gadiel Seroussi
发明人： Erik Ordentlich , Ron M. Roth , Gadiel Seroussi
IPC分类号： G06F12/00
CPC分类号： G11C16/00 , G11C7/1006 , G11C11/56 , G11C11/5628 , G11C11/5642 , G11C11/5685 , G11C13/004 , G11C13/0069
摘要： A data storage system including a memory array including a plurality of memory devices programmable in greater than two states. A memory control module may control operations of the memory array, and an encoder module may encode input data for storing to the memory array. The memory array may be an m×n memory array, and the memory control module may control operations of storing data to and retrieving data from the memory array.
摘要翻译：一种数据存储系统，包括存储器阵列，所述存储器阵列包括可在大于两个状态下编程的多个存储器件。存储器控制模块可以控制存储器阵列的操作，并且编码器模块可以编码用于存储到存储器阵列的输入数据。存储器阵列可以是m×n个存储器阵列，并且存储器控制模块可以控制将数据存储到存储器阵列中并从存储器阵列检索数据的操作。

4. 发明申请

US20130100727A1 OVERWRITING A MEMORY ARRAY 有权
标题翻译：重写内存阵列
公开(公告)号：US20130100727A1
公开(公告)日：2013-04-25
申请号：US13278882
申请日：2011-10-21
申请人： Erik Ordentlich , Ron M. Roth , Gadiel Seroussi
发明人： Erik Ordentlich , Ron M. Roth , Gadiel Seroussi
IPC分类号： G11C7/00 , G11C11/00
CPC分类号： G11C11/56 , G11C11/5628
摘要： A data storage system including a memory array including a plurality of memory devices programmable in greater than two states. A read/write control module may overwrite data in the memory array without violating a constraint during the overwrite process. The memory array may be an m×n memory array.
摘要翻译：一种数据存储系统，包括存储器阵列，所述存储器阵列包括可在大于两个状态下编程的多个存储器件。读/写控制模块可以覆盖存储器阵列中的数据，而不会在覆盖过程中违反约束。存储器阵列可以是m×n个存储器阵列。

5. 发明授权

US09015405B2 Method and system for encoding data for storage in a memory array 有权
标题翻译：用于编码存储在存储器阵列中的数据的方法和系统
公开(公告)号：US09015405B2
公开(公告)日：2015-04-21
申请号：US13805169
申请日：2010-06-29
申请人： Erik Ordentlich , Ron M. Roth , Gadiel Seroussi , Pascal Vontobel
发明人： Erik Ordentlich , Ron M. Roth , Gadiel Seroussi , Pascal Vontobel
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , G11C11/24 , G11C7/00 , G11C7/10 , G11C13/00 , G11C16/08 , G11C11/16 , G06F11/10 , G11C16/34
CPC分类号： G06F12/00 , G06F11/1008 , G11C7/1006 , G11C11/16 , G11C13/0007 , G11C13/0069 , G11C16/08 , G11C16/3418 , G11C2213/71 , G11C2213/77
摘要： A method of storing data into a memory array converts an input string into a first binary array with (m−1) rows and (n−1) columns. A second binary array with m rows and n columns in an encoded bit pattern is then generated from the first binary array. The second binary array in the encoded bit pattern has at most n/2 1's in each row and at most m/2 1's in each column, and the m-th row and an n-th column contain information for decoding other entries of the second binary array. The encoded bit pattern of the second binary array is then stored into corresponding memory devices of the memory array.
摘要翻译：将数据存储到存储器阵列中的方法将输入串转换为具有（m-1）行和（n-1）列的第一二进制数组。然后从第一个二进制数组生成第二个二进制数组，其中m行和n列位于编码位模式中。编码比特模式中的第二个二进制数组在每行中至多有n / 2 1，每列最多有m / 2 1，第m行和第n列包含用于解码第二个二进制数组。然后将第二二进制数组的编码位模式存储到存储器阵列的相应存储器件中。

6. 发明授权

US08537596B2 Overwriting a memory array 有权
标题翻译：覆盖内存阵列
公开(公告)号：US08537596B2
公开(公告)日：2013-09-17
申请号：US13278882
申请日：2011-10-21
申请人： Erik Ordentlich , Ron M. Roth , Gadiel Seroussi
发明人： Erik Ordentlich , Ron M. Roth , Gadiel Seroussi
IPC分类号： G11C11/00
CPC分类号： G11C11/56 , G11C11/5628
摘要： A data storage system including a memory array including a plurality of memory devices programmable in greater than two states. A read/write control module may overwrite data in the memory array without violating a constraint during the overwrite process. The memory array may be an m×n memory array.
摘要翻译：一种数据存储系统，包括存储器阵列，所述存储器阵列包括可在大于两个状态下编程的多个存储器件。读/写控制模块可以覆盖存储器阵列中的数据，而不会在覆盖过程中违反约束。存储器阵列可以是m×n个存储器阵列。

7. 发明申请

US20130097396A1 METHOD AND SYSTEM FOR ENCODING DATA FOR STORAGE IN A MEMORY ARRAY 有权
标题翻译：用于编码存储器阵列中的数据的方法和系统
公开(公告)号：US20130097396A1
公开(公告)日：2013-04-18
申请号：US13805169
申请日：2010-06-29
申请人： Erik Ordentlich , Ron M. Roth , Gadiel Seroussi , Pascal Vontobel
发明人： Erik Ordentlich , Ron M. Roth , Gadiel Seroussi , Pascal Vontobel
IPC分类号： G06F12/00
CPC分类号： G06F12/00 , G06F11/1008 , G11C7/1006 , G11C11/16 , G11C13/0007 , G11C13/0069 , G11C16/08 , G11C16/3418 , G11C2213/71 , G11C2213/77
摘要： A method of storing data into a memory array converts an input string into a first binary array with (m−1) rows and (n−1) columns. A second binary array with m rows and n columns in an encoded bit pattern is then generated from the first binary array. The second binary array in the encoded bit pattern has at most n/2 1's in each row and at most m/2 1's in each column, and the m-th row and an n-th column contain information for decoding other entries of the second binary array. The encoded bit pattern of the second binary array is then stored into corresponding memory devices of the memory array.
摘要翻译：将数据存储到存储器阵列中的方法将输入串转换为具有（m-1）行和（n-1）列的第一二进制数组。然后从第一个二进制数组生成第二个二进制数组，其中m行和n列位于编码位模式中。编码比特模式中的第二个二进制数组在每行中至多有n / 2 1，每列最多有m / 2 1，第m行和第n列包含用于解码第二个二进制数组。然后将第二二进制数组的编码位模式存储到存储器阵列的相应存储器件中。

8. 发明授权

US06532565B1 Burst error and additional random bit error correction in a memory 有权
标题翻译：存储器中的突发错误和附加随机位错误校正
公开(公告)号：US06532565B1
公开(公告)日：2003-03-11
申请号：US09440323
申请日：1999-11-15
申请人： Ron M. Roth , Gadiel Seroussi , Ian F. Blake
发明人： Ron M. Roth , Gadiel Seroussi , Ian F. Blake
IPC分类号： H03M1300
CPC分类号： G11C7/02 , G11C7/1006 , H03M13/15 , H03M13/17
摘要： A system for memory word error correction that enables correction of burst errors in memory words. The system is based on an adaptation of two-error correction BCH code which yields burst error correction without increasing the number of error correction bits in the memory words over prior two-error BCH code error correction schemes. The adaptation of two-error correction BCH code when combined with additional techniques for detecting columns of burst errors enables the correction of burst errors and additional random bit errors in memory words.
摘要翻译：一种用于存储器字错误校正的系统，其能够校正存储器字中的突发错误。该系统基于双纠错BCH码的适应，其产生突发错误校正，而不增加存储器字中的纠错位数超过先前的两误差BCH码纠错方案。当与用于检测突发错误列的附加技术组合时，双纠错BCH码的适应使得能够校正存储器字中的突发错误和附加的随机位错误。

9. 发明授权

US06466959B2 Apparatus and method for efficient arithmetic in finite fields through alternative representation 失效
标题翻译：通过替代表示在有限域中有效运算的装置和方法
公开(公告)号：US06466959B2
公开(公告)日：2002-10-15
申请号：US09751438
申请日：2001-02-26
申请人： Ian F. Blake , Ron M. Roth , Gadiel Seroussi
发明人： Ian F. Blake , Ron M. Roth , Gadiel Seroussi
IPC分类号： G06F700
CPC分类号： G06F7/724 , G06F7/726
摘要： A method and apparatus are shown for performing efficient arithmetic on binary vectors in a finite field. Typically, there is an efficient algorithm within an execution context, such as hardware or software, for performing a selected arithmetic operation on an operand. When the operand is in a first representative format and the efficient algorithm operates in an alternative representation format, then the operand is permutated from the first representative format to the alternative representation format. The efficient algorithm is then performed on the operand in the alternative representation format in order to obtain a result in the alternative representation format. The result is then permutated from the alternative representation format to the first representation format. Thus, efficient arithmetic is obtained by using the most efficient algorithm available in either the first representation format or the alternative representation format and permuting operands and results to the representation format corresponding to the most efficient algorithm available.
摘要翻译：示出了在有限域中对二进制向量执行有效运算的方法和装置。通常，在执行上下文（例如硬件或软件）中存在用于对操作数执行所选算术运算的有效算法。当操作数处于第一代表格式并且有效算法以替代表示格式操作时，则操作数从第一代表格式转换为替代表示格式。然后以替代表示格式对操作数执行有效的算法，以获得替代表示格式的结果。然后将结果从替代表示格式转换为第一表示格式。因此，通过使用以第一表示格式或替代表示格式可用的最有效的算法并且将操作数和结果替换为与可用的最有效算法相对应的表示格式而获得有效的算术。

10. 发明授权

US06199087B1 Apparatus and method for efficient arithmetic in finite fields through alternative representation 失效
公开(公告)号：US06199087B1
公开(公告)日：2001-03-06
申请号：US09104894
申请日：1998-06-25
申请人： Ian F. Blake , Ron M. Roth , Gadiel Seroussi
发明人： Ian F. Blake , Ron M. Roth , Gadiel Seroussi
IPC分类号： G06F738
CPC分类号： G06F7/724 , G06F7/726
摘要： A method and apparatus are shown for performing efficient arithmetic on binary vectors in a finite field. Typically, there is an efficient algorithm within an execution context, such as hardware or software, for performing a selected arithmetic operation on an operand. When the operand is in a first representative format and the efficient algorithm operates in an alternative representation format, then the operand is permutated from the first representative format to the alternative representation format. The efficient algorithm is then performed on the operand in the alternative representation format in order to obtain a result in the alternative representation format. The result is then permutated from the alternative representation format to the first representation format. Thus, efficient arithmetic is obtained by using the most efficient algorithm available in either the first representation format or the alternative representation format and permuting operands and results to the representation format corresponding to the most efficient algorithm available.

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