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1. 发明授权

US07585371B2 Substrate susceptors for receiving semiconductor substrates to be deposited upon 失效
标题翻译：用于接收要沉积的半导体衬底的衬底感受体
公开(公告)号：US07585371B2
公开(公告)日：2009-09-08
申请号：US10822093
申请日：2004-04-08
申请人： Eric R. Blomiley , Nirmal Ramaswamy , Ross S. Dando , Joel A. Drewes , Danny Dynka
发明人： Eric R. Blomiley , Nirmal Ramaswamy , Ross S. Dando , Joel A. Drewes , Danny Dynka
IPC分类号： C23C8/00 , C23C16/00
CPC分类号： C23C16/481 , C23C14/505 , C23C14/541 , C23C16/45521 , C23C16/4584 , C23C16/52 , C30B25/02 , C30B29/06
摘要： In one implementation, a substrate susceptor for receiving a semiconductor substrate for selective epitaxial silicon-comprising depositing thereon, where the depositing comprises measuring emissivity of the susceptor from at least one susceptor location in a non-contacting manner, includes a body having a front substrate receiving side, a back side, and a peripheral edge. At least one susceptor location from which emissivity is to be measured is received on at least one of the front substrate receiving side, the back side, and the edge. Such at least one susceptor location comprises an outermost surface comprising a material upon which selective epitaxial silicon will not deposit upon during selective epitaxial silicon depositing on a semiconductor substrate received by the susceptor for at least an initial thickness of epitaxial silicon depositing on said substrate. Other aspects and implementations are contemplated.
摘要翻译：在一个实施方案中，用于接收用于选择性外延硅的半导体衬底的衬底感受体包括沉积在其上，其中所述沉积包括以非接触方式从至少一个感受器位置测量所述基座的发射率，所述衬底基座包括具有前衬底接收侧，后侧和周缘。在前基板接收侧，后侧和边缘中的至少一个上接收要测量发射率的至少一个感受器位置。这样的至少一个感受器位置包括最外表面，其包括材料，选择性外延硅将不会沉积在选择性外延硅沉积在由基座接收的半导体衬底上，以至少沉积在所述衬底上的外延硅的初始厚度。考虑了其他方面和实现。

2. 发明授权

US07662649B2 Methods for assessing alignments of substrates within deposition apparatuses; and methods for assessing thicknesses of deposited layers within deposition apparatuses 失效
标题翻译：用于评估沉积设备内的衬底对准的方法; 以及用于评估沉积装置内的沉积层的厚度的方法
公开(公告)号：US07662649B2
公开(公告)日：2010-02-16
申请号：US11445032
申请日：2006-05-31
申请人： Eric R. Blomiley , Nirmal Ramaswamy , Ross S. Dando , Joel A. Drewes
发明人： Eric R. Blomiley , Nirmal Ramaswamy , Ross S. Dando , Joel A. Drewes
IPC分类号： H01L21/66
CPC分类号： H01L21/67115 , C23C16/481 , C23C16/52
摘要： The invention includes deposition apparatuses having reflectors with rugged reflective surfaces configured to disperse light reflected therefrom, and/or having dispersers between lamps and a substrate. The invention also includes optical methods for utilization within a deposition apparatus for assessing the alignment of a substrate within the apparatus and/or for assessing the thickness of a layer of material deposited within the apparatus.
摘要翻译：本发明包括具有反射器的沉积设备，其具有凹凸反射表面，其被配置为分散从其反射的光，和/或在灯和基板之间具有分散器。本发明还包括用于在沉积设备中利用的光学方法，用于评估设备内的衬底的对准和/或用于评估沉积在设备内的材料层的厚度。

3. 发明申请

US20080233700A1 Methods of forming integrated circuitry 审中-公开
标题翻译：形成集成电路的方法
公开(公告)号：US20080233700A1
公开(公告)日：2008-09-25
申请号：US11724784
申请日：2007-03-15
申请人： Eric R. Blomiley , Joel A. Drewes , D.V. Nirmal Ramaswamy
发明人： Eric R. Blomiley , Joel A. Drewes , D.V. Nirmal Ramaswamy
IPC分类号： H01L21/336
CPC分类号： H01L21/823425 , H01L21/823481 , H01L27/10873 , H01L27/1203
摘要： The invention includes semiconductor processing methods in which openings are formed to extend into a semiconductor substrate, and the substrate is then annealed around the openings to form cavities. The substrate is etched to expose the cavities, and the cavities are substantially filled with insulative material. The semiconductor substrate having the filled cavities therein can be utilized as a semiconductor-on-insulator-type structure, and transistor devices can be formed to be supported by the semiconductor material and to be over the cavities. In some aspects, the transistor devices have channel regions over the filled cavities, and in other aspects the transistor devices have source/drain regions over the filled cavities. The transistor devices can be incorporated into dynamic random access memory, and can be utilized in electronic systems.
摘要翻译：本发明包括半导体处理方法，其中形成开口以延伸到半导体衬底中，然后将衬底围绕开口退火以形成空腔。蚀刻衬底以暴露空腔，并且空腔基本上用绝缘材料填充。其中具有填充空穴的半导体衬底可以用作绝缘体上半导体型结构，并且晶体管器件可以形成为被半导体材料支撑并且在空腔之上。在一些方面，晶体管器件在填充腔体上具有沟道区域，在其它方面，晶体管器件在填充腔体上具有源极/漏极区域。晶体管器件可以并入到动态随机存取存储器中，并且可以在电子系统中使用。

4. 发明申请

US20070020876A1 Integrated circuitry, dynamic random access memory cells, electronic systems, and semiconductor processing methods 审中-公开
标题翻译：集成电路，动态随机存取存储器单元，电子系统和半导体处理方法
公开(公告)号：US20070020876A1
公开(公告)日：2007-01-25
申请号：US11185184
申请日：2005-07-19
申请人： Eric R. Blomiley , Joel A. Drewes , D. V. Nirmal Ramaswamy
发明人： Eric R. Blomiley , Joel A. Drewes , D. V. Nirmal Ramaswamy
IPC分类号： H01L21/76
CPC分类号： H01L21/823425 , H01L21/823481 , H01L27/10873 , H01L27/1203
摘要： The invention includes semiconductor processing methods in which openings are formed to extend into a semiconductor substrate, and the substrate is then annealed around the openings to form cavities. The substrate is etched to expose the cavities, and the cavities are substantially filled with insulative material. The semiconductor substrate having the filled cavities therein can be utilized as a semiconductor-on-insulator-type structure, and transistor devices can be formed to be supported by the semiconductor material and to be over the cavities. In some aspects, the transistor devices have channel regions over the filled cavities, and in other aspects the transistor devices have source/drain regions over the filled cavities. The transistor devices can be incorporated into dynamic random access memory, and can be utilized in electronic systems.
摘要翻译：本发明包括半导体处理方法，其中形成开口以延伸到半导体衬底中，然后将衬底围绕开口退火以形成空腔。蚀刻衬底以暴露空腔，并且空腔基本上用绝缘材料填充。其中具有填充空穴的半导体衬底可以用作绝缘体上半导体型结构，并且晶体管器件可以形成为被半导体材料支撑并且在空腔之上。在一些方面，晶体管器件在填充腔体上具有沟道区域，在其它方面，晶体管器件在填充腔体上具有源极/漏极区域。晶体管器件可以并入到动态随机存取存储器中，并且可以在电子系统中使用。

5. 发明授权

US07517758B2 Method of forming a vertical transistor 有权
标题翻译：形成垂直晶体管的方法
公开(公告)号：US07517758B2
公开(公告)日：2009-04-14
申请号：US11256430
申请日：2005-10-20
申请人： Nirmal Ramaswamy , Gurtej S. Sandhu , Cem Basceri , Eric R. Blomiley
发明人： Nirmal Ramaswamy , Gurtej S. Sandhu , Cem Basceri , Eric R. Blomiley
IPC分类号： H01L21/336
CPC分类号： H01L29/66787 , H01L21/02381 , H01L21/0245 , H01L21/02532 , H01L21/0262 , H01L29/66553 , H01L29/66666 , H01L29/7827 , H01L29/78642
摘要： The invention includes methods of forming epitaxial silicon-comprising material and methods of forming vertical transistors. In one implementation, a method of forming epitaxial silicon-comprising material includes providing a substrate comprising monocrystalline material. A first portion of the monocrystalline material is outwardly exposed while a second portion of the monocrystalline material is masked. A first silicon-comprising layer is epitaxially grown from the exposed monocrystalline material of the first portion and not from the monocrystalline material of the masked second portion. After growing the first silicon-comprising layer, the second portion of the monocrystalline material is unmasked. A second silicon-comprising layer is then epitaxially grown from the first silicon-comprising layer and from the unmasked monocrystalline material of the second portion. Other aspects and implementations are contemplated.
摘要翻译：本发明包括形成外延含硅材料的方法和形成垂直晶体管的方法。在一个实施方案中，形成外延含硅材料的方法包括提供包括单晶材料的衬底。单晶材料的第一部分向外暴露，而单晶材料的第二部分被掩蔽。第一含硅层从第一部分的暴露的单晶材料而不是被掩蔽的第二部分的单晶材料外延生长。在生长第一含硅层之后，单晶材料的第二部分被未掩蔽。然后从第一含硅层和第二部分的未掩模的单晶材料外延生长第二含硅层。考虑了其他方面和实现。

6. 发明授权

US07144779B2 Method of forming epitaxial silicon-comprising material 有权
标题翻译：形成外延含硅材料的方法
公开(公告)号：US07144779B2
公开(公告)日：2006-12-05
申请号：US10931924
申请日：2004-09-01
申请人： Nirmal Ramaswamy , Gurtej S. Sandhu , Cem Basceri , Eric R. Blomiley
发明人： Nirmal Ramaswamy , Gurtej S. Sandhu , Cem Basceri , Eric R. Blomiley
IPC分类号： H01L21/336
CPC分类号： H01L29/66787 , H01L21/02381 , H01L21/0245 , H01L21/02532 , H01L21/0262 , H01L29/66553 , H01L29/66666 , H01L29/7827 , H01L29/78642
摘要： The invention includes methods of forming epitaxial silicon-comprising material and methods of forming vertical transistors. In one implementation, a method of forming epitaxial silicon-comprising material includes providing a substrate comprising monocrystalline material. A first portion of the monocrystalline material is outwardly exposed while a second portion of the monocrystalline material is masked. A first silicon-comprising layer is epitaxially grown from the exposed monocrystalline material of the first portion and not from the monocrystalline material of the masked second portion. After growing the first silicon-comprising layer, the second portion of the monocrystalline material is unmasked. A second silicon-comprising layer is then epitaxially grown from the first silicon-comprising layer and from the unmasked monocrystalline material of the second portion. Other aspects and implementations are contemplated.
摘要翻译：本发明包括形成外延含硅材料的方法和形成垂直晶体管的方法。在一个实施方案中，形成外延含硅材料的方法包括提供包括单晶材料的衬底。单晶材料的第一部分向外暴露，而单晶材料的第二部分被掩蔽。第一含硅层从第一部分的暴露的单晶材料而不是被掩蔽的第二部分的单晶材料外延生长。在生长第一含硅层之后，单晶材料的第二部分被未掩蔽。然后从第一含硅层和第二部分的未掩模的单晶材料外延生长第二含硅层。考虑了其他方面和实现。

7. 发明授权

US07132355B2 Method of forming a layer comprising epitaxial silicon and a field effect transistor 有权
公开(公告)号：US07132355B2
公开(公告)日：2006-11-07
申请号：US10932129
申请日：2004-09-01
申请人： Nirmal Ramaswamy , Gurtej S. Sandhu , Cem Basceri , Eric R. Blomiley
发明人： Nirmal Ramaswamy , Gurtej S. Sandhu , Cem Basceri , Eric R. Blomiley
IPC分类号： H01L21/44
CPC分类号： H01L29/66787 , H01L21/0237 , H01L21/02381 , H01L21/02529 , H01L21/02532 , H01L21/0262 , H01L29/66742 , H01L29/78642
摘要： This invention includes methods of forming layers comprising epitaxial silicon, and field effect transistors. In one implementation, a method of forming a layer comprising epitaxial silicon comprises epitaxially growing a silicon-comprising layer from an exposed monocrystalline material. The epitaxially grown silicon comprises at least one of carbon, germanium, and oxygen present at a total concentration of no greater than 1 atomic percent. In one implementation, the layer comprises a silicon germanium alloy comprising at least 1 atomic percent germanium, and further comprises at least one of carbon and oxygen at a total concentration of no greater than 1 atomic percent. Other aspects and implementations are contemplated.

8. 发明授权

US06987055B2 Methods for deposition of semiconductor material 失效
标题翻译：半导体材料沉积方法
公开(公告)号：US06987055B2
公开(公告)日：2006-01-17
申请号：US10755000
申请日：2004-01-09
申请人： Eric R. Blomiley , Gurtej S. Sandhu , Cem Basceri , Nirmal Ramaswamy
发明人： Eric R. Blomiley , Gurtej S. Sandhu , Cem Basceri , Nirmal Ramaswamy
IPC分类号： H01L21/20 , H01L21/36
CPC分类号： H01L21/02381 , H01L21/02532 , H01L21/0262 , H01L21/02639
摘要： The invention includes a method for selective deposition of semiconductor material. A substrate is placed within a reaction chamber. The substrate comprises a first surface and a second surface. The first and second surfaces are exposed to a semiconductor material precursor under conditions in which growth of semiconductor material from the precursor comprises a lag phase prior to a growth phase, and under which it takes longer for the growth phase to initiate on the second surface than on the first surface. The exposure of the first and second surfaces is conducted for a time sufficient for the growth phase to occur on the first surface, but not long enough for the growth phase to occur on the second surface.
摘要翻译：本发明包括半导体材料的选择性沉积方法。将基板放置在反应室内。基板包括第一表面和第二表面。第一表面和第二表面在半导体材料前体暴露于其中来自前体的半导体材料的生长在生长阶段之前包含滞后期的条件下，并且在该阶段生长阶段在第二表面上开始需要更长时间比在第一个表面。进行第一表面和第二表面的曝光足够长的时间，以使生长阶段在第一表面上发生，但是不足以使生长相发生在第二表面上。

9. 发明授权

US07531395B2 Methods of forming a layer comprising epitaxial silicon, and methods of forming field effect transistors 有权
标题翻译：形成包含外延硅的层的方法以及形成场效应晶体管的方法
公开(公告)号：US07531395B2
公开(公告)日：2009-05-12
申请号：US11035298
申请日：2005-01-12
申请人： Eric R. Blomiley , Gurtej S. Sandhu , Cem Basceri , Nirmal Ramaswamy
发明人： Eric R. Blomiley , Gurtej S. Sandhu , Cem Basceri , Nirmal Ramaswamy
IPC分类号： H01L21/84 , H01L21/8238 , H01L21/336
CPC分类号： H01L29/66787 , H01L21/02381 , H01L21/0245 , H01L21/02532 , H01L21/0262 , H01L21/02642
摘要： Methods of forming layers comprising epitaxial silicon, and methods of forming field effect transistors are disclosed. A method of forming a layer comprising epitaxial silicon includes etching an opening into a silicate glass-comprising material received over a monocrystalline material. The etching is conducted to the monocrystalline material effective to expose the monocrystalline material at a base of the opening. A silicon-comprising layer is epitaxially grown within the opening from the monocrystalline material exposed at the base of the opening. The silicate glass-comprising material is etched from the substrate effective to leave a free-standing projection of the epitaxially grown silicon-comprising layer projecting from the monocrystalline material which was at the base of the opening. Other implementations and aspects are contemplated.
摘要翻译：公开了形成包含外延硅的层的方法和形成场效应晶体管的方法。形成包含外延硅的层的方法包括将开口蚀刻成通过单晶材料接收的含硅玻璃的材料。对单晶材料进行蚀刻，以有效地在开口的基部暴露单晶材料。在开口内从暴露在开口底部的单晶材料外延生长含硅层。从衬底上蚀刻含硅玻璃的材料有效地留下从开口底部的单晶材料突出的外延生长的含硅层的独立投影。考虑其他实现和方面。

10. 发明授权

US07439136B2 Method of forming a layer comprising epitaxial silicon 有权
标题翻译：形成包含外延硅的层的方法
公开(公告)号：US07439136B2
公开(公告)日：2008-10-21
申请号：US11730039
申请日：2007-03-29
申请人： Nirmal Ramaswamy , Gurtej S. Sandhu , Cem Basceri , Eric R. Blomiley
发明人： Nirmal Ramaswamy , Gurtej S. Sandhu , Cem Basceri , Eric R. Blomiley
IPC分类号： H01L21/336
CPC分类号： H01L29/66787 , H01L21/02381 , H01L21/0245 , H01L21/02532 , H01L21/0262 , H01L29/66553 , H01L29/66666 , H01L29/7827 , H01L29/78642
摘要： The invention includes methods of forming epitaxial silicon-comprising material and methods of forming vertical transistors. In one implementation, a method of forming epitaxial silicon-comprising material includes providing a substrate comprising monocrystalline material. A first portion of the monocrystalline material is outwardly exposed while a second portion of the monocrystalline material is masked. A first silicon-comprising layer is epitaxially grown from the exposed monocrystalline material of the first portion and not from the monocrystalline material of the masked second portion. After growing the first silicon-comprising layer, the second portion of the monocrystalline material is unmasked. A second silicon-comprising layer is then epitaxially grown from the first silicon-comprising layer and from the unmasked monocrystalline material of the second portion. Other aspects and implementations are contemplated.
摘要翻译：本发明包括形成外延含硅材料的方法和形成垂直晶体管的方法。在一个实施方案中，形成外延含硅材料的方法包括提供包括单晶材料的衬底。单晶材料的第一部分向外暴露，而单晶材料的第二部分被掩蔽。第一含硅层从第一部分的暴露的单晶材料而不是被掩蔽的第二部分的单晶材料外延生长。在生长第一含硅层之后，单晶材料的第二部分被未掩蔽。然后从第一含硅层和第二部分的未掩模的单晶材料外延生长第二含硅层。考虑了其他方面和实现。

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