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1. 发明申请

US20120306569A1 CHARGE SHARING TIME DOMAIN FILTER 有权
标题翻译：充电共享时域过滤器
公开(公告)号：US20120306569A1
公开(公告)日：2012-12-06
申请号：US13490110
申请日：2012-06-06
申请人： Eric Nestler , Jeffrey Venuti , Vladimir Zlatkovic , Kartik Nanda
发明人： Eric Nestler , Jeffrey Venuti , Vladimir Zlatkovic , Kartik Nanda
IPC分类号： H03K5/00
CPC分类号： H03K5/00 , H03H15/02
摘要： An approach to time domain filtering uses a passive charge sharing approach to implement an infinite impulse response filter. Delayed samples of an input signal are stored as charges on capacitors of a first array of capacitors, and delayed samples of the output signal are stored as charges on capacitors of a second array of capacitors. Outputs are determined by passively coupling capacitors of the first and second arrays to one another, and determining the output according to a total charge on the coupled capacitors. In some examples, a gain is applied to the total charge prior to storing the output on the second array of capacitors. In some examples, a charge scaling circuit is applied to the charges stored on the arrays prior to coupling capacitors to form the output.
摘要翻译：时域滤波方法采用无源电荷共享方式来实现无限脉冲响应滤波器。将输入信号的延迟样本作为电荷存储在第一电容器阵列的电容器上，并且输出信号的延迟采样作为电荷存储在第二电容器阵列的电容器上。输出由第一和第二阵列的电容器彼此无源耦合确定，并根据耦合的电容器上的总电荷来确定输出。在一些示例中，在将输出存储在第二电容器阵列之前，将增益应用于总电荷。在一些示例中，在耦合电容器之前，将电荷量化电路应用于存储在阵列上的电荷以形成输出。

2. 发明授权

US08717094B2 Charge sharing time domain filter 有权
标题翻译：电荷共享时域滤波器
公开(公告)号：US08717094B2
公开(公告)日：2014-05-06
申请号：US13490110
申请日：2012-06-06
申请人： Eric Nestler , Jeffrey Venuti , Vladimir Zlatkovic , Kartik Nanda
发明人： Eric Nestler , Jeffrey Venuti , Vladimir Zlatkovic , Kartik Nanda
IPC分类号： H03K5/00
CPC分类号： H03K5/00 , H03H15/02
摘要： An approach to time domain filtering uses a passive charge sharing approach to implement an infinite impulse response filter. Delayed samples of an input signal are stored as charges on capacitors of a first array of capacitors, and delayed samples of the output signal are stored as charges on capacitors of a second array of capacitors. Outputs are determined by passively coupling capacitors of the first and second arrays to one another, and determining the output according to a total charge on the coupled capacitors. In some examples, a gain is applied to the total charge prior to storing the output on the second array of capacitors. In some examples, a charge scaling circuit is applied to the charges stored on the arrays prior to coupling capacitors to form the output.
摘要翻译：时域滤波方法采用无源电荷共享方式来实现无限脉冲响应滤波器。将输入信号的延迟样本作为电荷存储在第一电容器阵列的电容器上，并且输出信号的延迟采样作为电荷存储在第二电容器阵列的电容器上。输出由第一和第二阵列的电容器彼此无源耦合确定，并根据耦合的电容器上的总电荷来确定输出。在一些示例中，在将输出存储在第二电容器阵列之前，将增益应用于总电荷。在一些示例中，在耦合电容器之前，将电荷量化电路应用于存储在阵列上的电荷以形成输出。

3. 发明授权

US08179731B2 Storage devices with soft processing 有权
公开(公告)号：US08179731B2
公开(公告)日：2012-05-15
申请号：US12537045
申请日：2009-08-06
申请人： Benjamin Vigoda , Eric Nestler , Jeffrey Bernstein , David Reynolds , Alexander Alexeyev , Jeffrey Venuti , William Bradley , Vladimir Zlatkovic
发明人： Benjamin Vigoda , Eric Nestler , Jeffrey Bernstein , David Reynolds , Alexander Alexeyev , Jeffrey Venuti , William Bradley , Vladimir Zlatkovic
IPC分类号： G11C7/00
CPC分类号： G11C7/00 , G11C7/1006 , G11C7/16 , G11C11/24 , G11C11/5642 , G11C16/04 , G11C27/005 , G11C29/00
摘要： A storage device includes a storage array having a group of storage elements. Each storage element can written to a discrete set of physical states. A read circuit selects one or more storage elements and generates, for each selected storage element, an analog signal representative of the physical state of the selected storage element. A signal processing circuit processes the analog signal to generate a plurality of outputs, with each output representing a degree of an association of the selected storage element with a different subset of one or more of the discrete set of physical states.

4. 发明授权

US08107306B2 Storage devices with soft processing 有权
标题翻译：软处理存储设备
公开(公告)号：US08107306B2
公开(公告)日：2012-01-31
申请号：US12537081
申请日：2009-08-06
申请人： Benjamin Vigoda , Eric Nestler , Jeffrey Bernstein , David Reynolds , Alexander Alexeyev , Jeffrey Venuti , William Bradley , Vladimir Zlatkovic
发明人： Benjamin Vigoda , Eric Nestler , Jeffrey Bernstein , David Reynolds , Alexander Alexeyev , Jeffrey Venuti , William Bradley , Vladimir Zlatkovic
IPC分类号： G11C7/00
CPC分类号： G11C7/00 , G11C7/1006 , G11C7/16 , G11C11/24 , G11C11/5642 , G11C16/04 , G11C27/005 , G11C29/00
摘要： A storage device includes a storage array having a group of storage elements. Each storage element can written to a discrete set of physical states. A read circuit selects one or more storage elements and generates, for each selected storage element, an analog signal representative of the physical state of the selected storage element. A signal processing circuit processes the analog signal to generate a plurality of outputs, with each output representing a degree of an association of the selected storage element with a different subset of one or more of the discrete set of physical states.
摘要翻译：存储装置包括具有一组存储元件的存储阵列。每个存储元件可以写入一组离散的物理状态。读取电路选择一个或多个存储元件，并为每个选定的存储元件生成表示所选存储元件的物理状态的模拟信号。信号处理电路处理模拟信号以产生多个输出，其中每个输出表示所选择的存储元件与离散的物理状态集合中的一个或多个的不同子集的关联程度。

5. 发明授权

US09036420B2 Storage devices with soft processing 有权
标题翻译：软处理存储设备
公开(公告)号：US09036420B2
公开(公告)日：2015-05-19
申请号：US13471816
申请日：2012-05-15
申请人： Benjamin Vigoda , Jeffrey Bernstein , Jeffrey Venuti , Alexander Alexeyev , Eric Nestler , David Reynolds , William Bradley , Vladimir Zlatkovic
发明人： Benjamin Vigoda , Jeffrey Bernstein , Jeffrey Venuti , Alexander Alexeyev , Eric Nestler , David Reynolds , William Bradley , Vladimir Zlatkovic
IPC分类号： G11C16/04 , G11C7/00 , G11C7/10 , G11C7/16 , G11C11/56 , G11C27/00 , G11C11/24 , G11C29/00
CPC分类号： G11C7/00 , G11C7/1006 , G11C7/16 , G11C11/24 , G11C11/5642 , G11C16/04 , G11C27/005 , G11C29/00
摘要： A storage device includes a storage array having a group of storage elements. Each storage element can written to a discrete set of physical states. A read circuit selects one or more storage elements and generates, for each selected storage element, an analog signal representative of the physical state of the selected storage element. A signal processing circuit processes the analog signal to generate a plurality of outputs, with each output representing a degree of an association of the selected storage element with a different subset of one or more of the discrete set of physical states.
摘要翻译：存储装置包括具有一组存储元件的存储阵列。每个存储元件可以写入一组离散的物理状态。读取电路选择一个或多个存储元件，并为每个选定的存储元件生成表示所选存储元件的物理状态的模拟信号。信号处理电路处理模拟信号以产生多个输出，其中每个输出表示所选择的存储元件与离散的物理状态集合中的一个或多个的不同子集的关联程度。

6. 发明授权

US08547272B2 Charge sharing analog computation circuitry and applications 有权
标题翻译：电荷共享模拟计算电路和应用
公开(公告)号：US08547272B2
公开(公告)日：2013-10-01
申请号：US13813101
申请日：2011-08-18
申请人： Eric Nestler , Vladimir Zlatkovic , Jeffrey Venuti
发明人： Eric Nestler , Vladimir Zlatkovic , Jeffrey Venuti
IPC分类号： H03M1/12
CPC分类号： H03H7/0138 , G06F17/5063 , G10K15/00 , H02M1/14 , H03H15/00 , H03H15/02 , H03M1/12 , H04R25/00
摘要： In one aspect, reduced power consumption and/or circuit area of a discrete time analog signal processing module is achieved in an approach that makes use of entirely, or largely, passive charge sharing circuitry, which may include configurable (e.g., after fabrication, at runtime) multiplicative scaling stages that do not require active devices in the signal path. In some examples, multiplicative coefficients are represented digitally, and are transformed to configure the reconfigurable circuitry to achieve a linear relationship between a desired coefficient and a degree of charge transfer. In some examples, multiple successive charge sharing phases are used to achieve a desired multiplicative effect that provides a large dynamic range of coefficients without requiring a commensurate range of sizes of capacitive elements. The scaling circuits can be combined to form configurable time domain or frequency domain filters.
摘要翻译：在一个方面，离散时间模拟信号处理模块的降低的功耗和/或电路面积是通过使用完全或很大程度上被动电荷共享电路的方法实现的，其中可能包括可配置（例如，在制造之后，在运行时）乘法缩放阶段，不需要信号路径中的有源设备。在一些示例中，乘法系数被数字地表示，并且被变换以配置可重构电路以实现期望系数和电荷转移程度之间的线性关系。在一些示例中，使用多个连续的电荷共享阶段来实现期望的乘法效应，其提供大的动态范围的系数，而不需要电容元件尺寸的相应范围。缩放电路可以组合以形成可配置的时域或频域滤波器。

7. 发明申请

US20130207827A1 CHARGE SHARING ANALOG COMPUTATION CIRCUITRY AND APPLICATIONS 有权
标题翻译：充电共享模拟计算电路和应用
公开(公告)号：US20130207827A1
公开(公告)日：2013-08-15
申请号：US13813101
申请日：2011-08-18
申请人： Eric Nestler , Vladimir Zlatkovic , Jeffrey Venuti
发明人： Eric Nestler , Vladimir Zlatkovic , Jeffrey Venuti
IPC分类号： H03H15/00 , H03M1/12
CPC分类号： H03H7/0138 , G06F17/5063 , G10K15/00 , H02M1/14 , H03H15/00 , H03H15/02 , H03M1/12 , H04R25/00
摘要： In one aspect, reduced power consumption and/or circuit area of a discrete time analog signal processing module is achieved in an approach that makes use of entirely, or largely, passive charge sharing circuitry, which may include configurable (e.g., after fabrication, at runtime) multiplicative scaling stages that do not require active devices in the signal path. In some examples, multiplicative coefficients are represented digitally, and are transformed to configure the reconfigurable circuitry to achieve a linear relationship between a desired coefficient and a degree of charge transfer. In some examples, multiple successive charge sharing phases are used to achieve a desired multiplicative effect that provides a large dynamic range of coefficients without requiring a commensurate range of sizes of capacitive elements. The scaling circuits can be combined to form configurable time domain or frequency domain filters.
摘要翻译：在一个方面，离散时间模拟信号处理模块的降低的功耗和/或电路面积是通过使用完全或很大程度上被动电荷共享电路的方法实现的，其中可能包括可配置（例如，在制造之后，在运行时）乘法缩放阶段，不需要信号路径中的有源设备。在一些示例中，乘法系数被数字地表示，并且被变换以配置可重构电路以实现期望系数和电荷转移程度之间的线性关系。在一些示例中，使用多个连续的电荷共享阶段来实现期望的乘法效应，其提供大的动态范围的系数，而不需要电容元件尺寸的相应范围。缩放电路可以组合以形成可配置的时域或频域滤波器。

8. 发明申请

US20100220514A1 STORAGE DEVICES WITH SOFT PROCESSING 审中-公开
公开(公告)号：US20100220514A1
公开(公告)日：2010-09-02
申请号：US12537060
申请日：2009-08-06
申请人： Benjamin Vigoda , Jeffrey Bernstein , Jeffrey Venuti , Alexander Alexeyev , Eric Nestler , David Reynolds
发明人： Benjamin Vigoda , Jeffrey Bernstein , Jeffrey Venuti , Alexander Alexeyev , Eric Nestler , David Reynolds
IPC分类号： G11C11/24 , G11C7/00
CPC分类号： G11C27/005 , G11C7/16 , G11C8/10 , G11C11/5642 , G11C11/5678 , G11C13/0004 , G11C13/0064 , G11C13/0069 , G11C29/00 , G11C2013/0092 , G11C2211/5634
摘要： A storage device includes a storage array having a group of storage elements. Each storage element can written to a discrete set of physical states. A read circuit selects one or more storage elements and generates, for each selected storage element, an analog signal representative of the physical state of the selected storage element. A signal processing circuit processes the analog signal to generate a plurality of outputs, with each output representing a degree of an association of the selected storage element with a different subset of one or more of the discrete set of physical states.

9. 发明申请

US20130094298A1 STORAGE DEVICES WITH SOFT PROCESSING 有权
标题翻译：具有软处理的存储设备
公开(公告)号：US20130094298A1
公开(公告)日：2013-04-18
申请号：US13471816
申请日：2012-05-15
申请人： Benjamin Vigoda , Eric Nestler , Jeffrey Bernstein , David Reynolds , Alexander Alexeyev , Jeffrey Venuti , William Bradley , Vladimir Ziatkovic
发明人： Benjamin Vigoda , Eric Nestler , Jeffrey Bernstein , David Reynolds , Alexander Alexeyev , Jeffrey Venuti , William Bradley , Vladimir Ziatkovic
IPC分类号： G11C7/00 , G11C16/04 , G11C11/24
CPC分类号： G11C7/00 , G11C7/1006 , G11C7/16 , G11C11/24 , G11C11/5642 , G11C16/04 , G11C27/005 , G11C29/00
摘要： A storage device includes a storage array having a group of storage elements. Each storage element can written to a discrete set of physical states. A read circuit selects one or more storage elements and generates, for each selected storage element, an analog signal representative of the physical state of the selected storage element. A signal processing circuit processes the analog signal to generate a plurality of outputs, with each output representing a degree of an association of the selected storage element with a different subset of one or more of the discrete set of physical states.
摘要翻译：存储装置包括具有一组存储元件的存储阵列。每个存储元件可以写入一组离散的物理状态。读取电路选择一个或多个存储元件，并为每个选定的存储元件生成表示所选存储元件的物理状态的模拟信号。信号处理电路处理模拟信号以产生多个输出，其中每个输出表示所选择的存储元件与离散的物理状态集合中的一个或多个的不同子集的关联程度。

10. 发明申请

US20100281089A1 SIGNAL MAPPING 有权
标题翻译：信号映射
公开(公告)号：US20100281089A1
公开(公告)日：2010-11-04
申请号：US12716113
申请日：2010-03-02
申请人： Benjamin Vigoda , Jeffrey Bernstein , Alexander Alexeyev , Jeffrey Venuti
发明人： Benjamin Vigoda , Jeffrey Bernstein , Alexander Alexeyev , Jeffrey Venuti
IPC分类号： G06F1/02 , G06G7/18 , G06F17/14
CPC分类号： H04L27/38 , H03M1/368
摘要： A circuit includes a signal processing circuit for accepting an input and for generating a set of outputs. The input is provided in an input range that has a set of representative values, and each output represents a measure of an association of the input with one or more of the representative values. The signal processing circuit includes a group of output sections, each output section being responsive to the input of the signal processing circuit. Each output section includes one or more sigmoid generators. Each sigmoid generator is responsive to an input of the output section to generate an output that represents a sigmoid function of the input of the output section. Each output section also includes a circuitry for combining the outputs of the one or more sigmoid generators to form one of the set of outputs of the signal processing circuit. An input transformation circuit is coupled to the plurality of output sections. The input transformation circuit is configurable to transform the input of the signal processing circuit for controlling a mapping characteristic from the input to the set of outputs.
摘要翻译：电路包括用于接受输入并产生一组输出的信号处理电路。在具有一组代表值的输入范围中提供输入，并且每个输出表示输入与一个或多个代表值的关联度量。信号处理电路包括一组输出部分，每个输出部分响应信号处理电路的输入。每个输出部分包括一个或多个S形发生器。每个S形发生器响应于输出部分的输入以产生表示输出部分的输入的S形功能的输出。每个输出部分还包括用于组合一个或多个S形发生器的输出以形成信号处理电路的一组输出的电路。输入变换电路耦合到多个输出部分。输入变换电路可配置为变换信号处理电路的输入，用于控制从输入到输出组的映射特性。

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