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1. 发明授权

US07348909B2 Reconfigurable mixed-signal VLSI implementation of distributed arithmetic 有权
标题翻译：可重构混合信号VLSI实现分布式算术
公开(公告)号：US07348909B2
公开(公告)日：2008-03-25
申请号：US11465192
申请日：2006-08-17
申请人： Erhan Ozalevli , Paul Hasler , David Verl Anderson , Walter Geeshan Huang
发明人： Erhan Ozalevli , Paul Hasler , David Verl Anderson , Walter Geeshan Huang
IPC分类号： H03M1/66
CPC分类号： H03M1/662
摘要： Disclosed herein is a reconfigurable mixed signal distributed arithmetic system including: an array of tunable voltage references operable for receiving a delayed digital input signal; a combination device in electrical communication with the array of tunable floating-gate voltage references that selectively combines an output of the array of tunable voltage references into an analog output signal; and a feedback element in electrical communication with the combination device, wherein the array of tunable voltages and the delayed digital input signal combine to perform a distributed arithmetic function and the reconfigurable mixed signal distributed arithmetic system responsively generates the analog output signal.
摘要翻译：这里公开了一种可重新配置的混合信号分布式运算系统，包括：可调谐电压基准阵列，可操作用于接收延迟的数字输入信号; 与可调谐浮栅电压基准阵列电连通的组合装置，其选择性地将可调电压基准阵列的输出组合成模拟输出信号; 以及与所述组合装置电通信的反馈元件，其中所述可调谐电压阵列和所述延迟数字输入信号组合以执行分布式算术功能，并且所述可重构混合信号分布式运算系统响应地产生所述模拟输出信号。

2. 发明申请

US20120263261A1 INCREMENTAL LATTICE REDUCTION SYSTEMS AND METHODS 有权
标题翻译：增量减少系统和方法
公开(公告)号：US20120263261A1
公开(公告)日：2012-10-18
申请号：US13325242
申请日：2011-12-14
申请人： Brian Gestner , David Verl Anderson , Xiaoli Ma
发明人： Brian Gestner , David Verl Anderson , Xiaoli Ma
IPC分类号： H04L27/00
CPC分类号： H04L25/03203 , H04L25/03242 , H04L25/03305 , H04L2025/03426
摘要： An exemplary embodiment of the present invention provides an incremental lattice reduction method comprising: receiving an input signal at a plurality of input terminals; evaluating a reliability assessment condition using a primary symbol vector estimate of at least a portion of the input signal; terminating the incremental lattice reduction method if the reliability assessment condition is satisfied; and if the reliability assessment condition is not satisfied, performing at least one iteration of a lattice reduction detection sub-method to obtain a secondary symbol vector estimate.
摘要翻译：本发明的一个示例性实施例提供一种增量格点简化方法，包括：在多个输入端接收输入信号; 使用所述输入信号的至少一部分的主符号向量估计来评估可靠性评估条件; 如果满足可靠性评估条件，则终止增量格点退化方法; 并且如果不满足可靠性评估条件，则进行格子缩小检测子方法的至少一次迭代以获得二次符号向量估计。

3. 发明授权

US08559544B2 Systems and methods for lattice reduction 有权
标题翻译：晶格退化的系统和方法
公开(公告)号：US08559544B2
公开(公告)日：2013-10-15
申请号：US12943824
申请日：2010-11-10
申请人： David Verl Anderson , Brian Joseph Gestner , Wei Zhang , Xiaoli Ma
发明人： David Verl Anderson , Brian Joseph Gestner , Wei Zhang , Xiaoli Ma
IPC分类号： H04B7/02 , G06F15/80
CPC分类号： H04B7/0854
摘要： Disclosed herein are lattice reduction systems and methods for a MIMO communication system. One such method includes providing a channel matrix corresponding to a channel in a MIMO communication system, preprocessing the channel matrix to form at least an upper triangular matrix, implementing a relaxed size reduction process, and implementing a basis update process. Implementing the relaxed size reduction process comprises choosing a first relaxed size reduction parameter for a first-off-diagonal element of the upper triangular matrix, choosing a second relaxed size reduction parameter, which is greater than the first relaxed size reduction parameter, for a second-off-diagonal element of the upper triangular matrix evaluating whether a first relaxed size reduction condition is satisfied for the first-off-diagonal element of the upper triangular matrix, and evaluating whether a second relaxed size reduction condition is satisfied for the second-off-diagonal element of the upper triangular matrix.
摘要翻译：这里公开了用于MIMO通信系统的晶格简化系统和方法。一种这样的方法包括提供与MIMO通信系统中的信道相对应的信道矩阵，预处理信道矩阵以形成至少上三角矩阵，实现松弛尺寸减小过程，以及实现基本更新过程。实现松弛尺寸减小过程包括为上三角矩阵选择第一松弛尺寸缩小参数，为第二松弛尺寸选择大于第一松弛尺寸减小参数的第二松弛尺寸减小参数评估上三角矩阵的第一对角线元素是否满足第一松弛尺寸缩小条件，以及评估第二松弛尺寸缩小条件是否满足二次关系的上三角矩阵的非对角线元素上三角矩阵的方形元素。

4. 发明授权

US08948318B2 Incremental lattice reduction systems and methods 有权
标题翻译：增量晶格还原系统和方法
公开(公告)号：US08948318B2
公开(公告)日：2015-02-03
申请号：US13325242
申请日：2011-12-14
申请人： Brian Gestner , David Verl Anderson , Xiaoli Ma
发明人： Brian Gestner , David Verl Anderson , Xiaoli Ma
IPC分类号： H04L27/06 , H04L25/03
CPC分类号： H04L25/03203 , H04L25/03242 , H04L25/03305 , H04L2025/03426
摘要： An exemplary embodiment of the present invention provides an incremental lattice reduction method comprising: receiving an input signal at a plurality of input terminals; evaluating a reliability assessment condition using a primary symbol vector estimate of at least a portion of the input signal; terminating the incremental lattice reduction method if the reliability assessment condition is satisfied; and if the reliability assessment condition is not satisfied, performing at least one iteration of a lattice reduction detection sub-method to obtain a secondary symbol vector estimate.
摘要翻译：本发明的一个示例性实施例提供一种增量格点简化方法，包括：在多个输入端接收输入信号; 使用所述输入信号的至少一部分的主符号向量估计来评估可靠性评估条件; 如果满足可靠性评估条件，则终止增量格点退化方法; 并且如果不满足可靠性评估条件，则进行格子缩小检测子方法的至少一次迭代以获得二次符号向量估计。

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