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1. 发明授权

US09391009B2 Semiconductor packages including heat exhaust part 有权
标题翻译：半导体封装包括散热部件
公开(公告)号：US09391009B2
公开(公告)日：2016-07-12
申请号：US14289900
申请日：2014-05-29
申请人： Eon Soo Jang , Kyol Park , Jongwoo Park , Jin-Kwon Bae , Yunhyeok Im , Jichul Kim , Soojae Park
发明人： Eon Soo Jang , Kyol Park , Jongwoo Park , Jin-Kwon Bae , Yunhyeok Im , Jichul Kim , Soojae Park
IPC分类号： H01L23/36 , H01L23/498 , H01L25/065 , H01L25/10 , H01L25/00 , H01L23/433 , H01L23/00
CPC分类号： H01L23/49816 , H01L23/36 , H01L23/4334 , H01L24/73 , H01L25/0652 , H01L25/105 , H01L25/50 , H01L2224/16145 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/48091 , H01L2224/48227 , H01L2224/73204 , H01L2224/73253 , H01L2224/73265 , H01L2225/0651 , H01L2225/06517 , H01L2225/06562 , H01L2225/06568 , H01L2225/06572 , H01L2225/06589 , H01L2225/1023 , H01L2225/1058 , H01L2225/1094 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/18161 , H01L2924/00012 , H01L2924/00
摘要： According to example embodiments, a semiconductor package includes a lower package, upper packages on the lower package and laterally spaced apart from each other, a lower heat exhaust part between the lower package and the upper packages, an intermediate heat exhaust part between the upper packages and connected to the lower heat exhaust part, and an upper heat exhaust part on the upper packages and connected to the intermediate heat exhaust part.
摘要翻译：根据示例实施例，半导体封装包括下封装，下封装上的上封装并且彼此横向间隔开，下封装和上封装之间的下热排出部分，位于上封装之间的中间热排出部并连接到下部散热部，以及上部热封装上的上部散热部，并与中间散热部连接。

2. 发明授权

US07516674B1 Method and apparatus for thermally induced testing of materials under transient temperature 失效
标题翻译：在瞬态温度下对材料进行热诱导测试的方法和装置
公开(公告)号：US07516674B1
公开(公告)日：2009-04-14
申请号：US12198479
申请日：2008-08-26
申请人： Claudius Feger , Soojae Park
发明人： Claudius Feger , Soojae Park
IPC分类号： G01N19/08
CPC分类号： G01N3/60 , G01N2203/0066 , G01N2203/0073 , G01N2203/027
摘要： A method for measuring the fracture and fatigue crack growth behavior of a material includes heating at least one sample having a first end and a second end and a pre-applied crack between the first end and the second end; heating a fixture having a lower coefficient of thermal expansion than said at least one sample; attaching the first end and the second end of the at least one sample to the fixture; cooling the at least one sample and fixture; recording the temperature at which propagation of the pre-applied crack through the width of the at least one sample occurs as the critical fracture temperature; for a plurality of samples, each sample having a different ratio of pre-applied crack length to sample width, determining the critical fracture temperature as a function of said ratio; and ranking materials by the critical fracture temperature.
摘要翻译：用于测量材料的断裂和疲劳裂纹扩展行为的方法包括加热至少一个具有第一端和第二端的样品和在第一端和第二端之间的预应力裂纹; 加热具有比所述至少一个样品更低的热膨胀系数的固定装置; 将所述至少一个样品的第一端和第二端附接到所述夹具; 冷却至少一个样品和固定装置; 记录预先施加的裂纹的传播通过至少一个样品的宽度的温度作为临界断裂温度; 对于多个样品，每个样品具有不同的预先施加的裂纹长度与样品宽度的比率，确定临界裂纹温度作为所述比例的函数; 并按临界断裂温度对材料进行排序。

3. 发明申请

US20120292375A1 METHOD OF JOINING A CHIP ON A SUBSTRATE 审中-公开
标题翻译：在基板上接合芯片的方法
公开(公告)号：US20120292375A1
公开(公告)日：2012-11-22
申请号：US13566467
申请日：2012-08-03
申请人： Pascal P. Blais , Paul F. Fortier , Kang-Wook Lee , Jae-Woong Nah , Soojae Park , Robert L. Toutant , Alain A. Warren
发明人： Pascal P. Blais , Paul F. Fortier , Kang-Wook Lee , Jae-Woong Nah , Soojae Park , Robert L. Toutant , Alain A. Warren
IPC分类号： B23K37/04
CPC分类号： B23K1/0016 , H01L21/563 , H01L24/75 , H01L24/81 , H01L2224/13099 , H01L2224/131 , H01L2224/73204 , H01L2224/75704 , H01L2224/75985 , H01L2224/81005 , H01L2224/81191 , H01L2224/81815 , H01L2224/8191 , H01L2924/01006 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01076 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/10253 , H01L2924/15787 , H01L2924/3511 , H01L2924/01026 , H01L2924/00
摘要： A method and apparatus for making chip assemblies is disclosed that prevent or reduce the cracking and delamination of ultra low-k dielectrics in the back-end-of-line in Si chips that can occur during the chip assembly process. The method and apparatus apply pressure to the top and bottom surfaces of a substrate during the chip bonding process so that the bending and warping of the assembled modules are reduced. The reduced bending and warping prevent or reduce the cracking and delamination of ultra low-k dielectrics.
摘要翻译：公开了一种用于制造芯片组件的方法和装置，其防止或减少在芯片组装过程中可能发生的Si芯片中后端的超低k电介质的开裂和分层。该方法和装置在芯片接合过程期间对基板的顶表面和底表面施加压力，使得组装的模块的弯曲和翘曲减小。减小的弯曲和翘曲防止或减少超低k电介质的开裂和分层。

4. 发明授权

US08269340B2 Curvilinear heat spreader/lid with improved heat dissipation 失效
标题翻译：曲线散热器/盖具有改善的散热
公开(公告)号：US08269340B2
公开(公告)日：2012-09-18
申请号：US11857812
申请日：2007-09-19
申请人： Michael A. Gaynes , Maurice McGlashan-Powell , Soojae Park , Edward Yarmchuk
发明人： Michael A. Gaynes , Maurice McGlashan-Powell , Soojae Park , Edward Yarmchuk
IPC分类号： H01L23/34 , H01L23/10
CPC分类号： H01L23/42 , H01L2224/05573 , H01L2224/16 , H01L2224/73253 , H01L2924/10253 , H01L2924/3511 , H01L2924/00
摘要： A heat spreader or lid for a microelectronic package, in which the heat spreader has an underside surface that includes at least one curvilinear contour, in which the curvilinear contour is selected from at least one positive or protruding curvilinear feature, at least one negative or recessed curvilinear feature, and a combination thereof. A microelectronic package that includes the heat spreader/lid, in which there is improved heat dissipation or reduced mechanical stress in an interface between the heat spreader/lid and a circuit chip.
摘要翻译：一种用于微电子封装的散热器或盖，其中散热器具有包括至少一个曲线轮廓的下表面，其中曲线轮廓选自至少一个正或突出的曲线特征，至少一个负或凹入曲线特征及其组合。包括散热器/盖的微电子封装，其中在散热器/盖和电路芯片之间的界面中改善了散热或降低了机械应力。

5. 发明申请

US20090072387A1 CURVILINEAR HEAT SPREADER/LID WITH IMPROVED HEAT DISSIPATION 失效
标题翻译： CURVILINEAR热传播器/带有改进的散热器
公开(公告)号：US20090072387A1
公开(公告)日：2009-03-19
申请号：US11857812
申请日：2007-09-19
申请人： Michael A. Gaynes , Maurice McGlashan-Powell , Soojae Park , Edward Yarmchuk
发明人： Michael A. Gaynes , Maurice McGlashan-Powell , Soojae Park , Edward Yarmchuk
IPC分类号： H01L23/34
CPC分类号： H01L23/42 , H01L2224/05573 , H01L2224/16 , H01L2224/73253 , H01L2924/10253 , H01L2924/3511 , H01L2924/00
摘要： A heat spreader or lid for a microelectronic package, in which the heat spreader has an underside surface that includes at least one curvilinear contour, in which the curvilinear contour is selected from at least one positive or protruding curvilinear feature, at least one negative or recessed curvilinear feature, and a combination thereof. A microelectronic package that includes the heat spreader/lid, in which there is improved heat dissipation or reduced mechanical stress in an interface between the heat spreader/lid and a circuit chip.
摘要翻译：一种用于微电子封装的散热器或盖，其中散热器具有包括至少一个曲线轮廓的下表面，其中曲线轮廓选自至少一个正或突出的曲线特征，至少一个负或凹入曲线特征及其组合。包括散热器/盖的微电子封装，其中在散热器/盖和电路芯片之间的界面中改善了散热或降低了机械应力。

6. 发明授权

US08352230B2 Integrated framework for finite-element methods for package, device and circuit co-design 有权
标题翻译：用于封装，器件和电路协同设计的有限元方法的集成框架
公开(公告)号：US08352230B2
公开(公告)日：2013-01-08
申请号：US12723130
申请日：2010-03-12
申请人： Keunwoo Kim , Soojae Park
发明人： Keunwoo Kim , Soojae Park
IPC分类号： G06F17/50 , G06G7/62
CPC分类号： G06F17/50 , G06F17/5018 , G06F17/5036 , G06F2217/40 , G06F2217/78 , G06F2217/80
摘要： Electrical finite element analysis is carried out on a circuit design, which includes devices, to determine an acceptable power-performance envelope and to obtain data for circuit temperature mapping. A circuit temperature map is developed for the circuit design, based on the data for circuit temperature mapping. Thermo-mechanical finite element analysis is carried out on a package design for the circuit design, based on the circuit temperature map, to determine a package reliability limit based on thermal stress considerations. It is determined whether the package design and the circuit design jointly satisfy: (i) power-performance conditions specified in the acceptable power-performance envelope; and (ii) the package reliability limit based on the thermal stress considerations.
摘要翻译：电气有限元分析在包括设备的电路设计中进行，以确定可接受的功率性能包络并获得电路温度映射的数据。基于电路温度映射的数据，开发了电路设计的电路温度图。基于电路温度图对电路设计的封装设计进行热机械有限元分析，以确定基于热应力考虑的封装可靠性限制。确定包装设计和电路设计是否共同满足：（i）在可接受的功率性能包络中指定的功率性能条件; 和（ii）基于热应力考虑的封装可靠性限制。

7. 发明申请

US20120309132A1 CURVILINEAR HEAT SPREADER/LID WITH IMPROVED HEAT DISSIPATION 审中-公开
标题翻译： CURVILINEAR热传播器/带有改进的散热器
公开(公告)号：US20120309132A1
公开(公告)日：2012-12-06
申请号：US13586421
申请日：2012-08-15
申请人： Michael A. Gaynes , Maurice McGlashan-Powell , Soojae Park , Edward Yarmchuk
发明人： Michael A. Gaynes , Maurice McGlashan-Powell , Soojae Park , Edward Yarmchuk
IPC分类号： B65D51/00 , H01L21/50
CPC分类号： H01L23/42 , H01L2224/05573 , H01L2224/16 , H01L2224/73253 , H01L2924/10253 , H01L2924/3511 , H01L2924/00
摘要： A heat spreader or lid for a microelectronic package, in which the heat spreader has an underside surface that includes at least one curvilinear contour, in which the curvilinear contour is selected from at least one positive or protruding curvilinear feature, at least one negative or recessed curvilinear feature, and a combination thereof. A microelectronic package that includes the heat spreader/lid, in which there is improved heat dissipation or reduced mechanical stress in an interface between the heat spreader/lid and a circuit chip.
摘要翻译：一种用于微电子封装的散热器或盖，其中散热器具有包括至少一个曲线轮廓的下表面，其中曲线轮廓选自至少一个正或突出的曲线特征，至少一个负或凹入曲线特征及其组合。包括散热器/盖的微电子封装，其中在散热器/盖和电路芯片之间的界面中改善了散热或降低了机械应力。

8. 发明申请

US20110049221A1 METHOD OF JOINING A CHIP ON A SUBSTRATE 有权
标题翻译：在基板上接合芯片的方法
公开(公告)号：US20110049221A1
公开(公告)日：2011-03-03
申请号：US12551960
申请日：2009-09-01
申请人： Pascal P. Blais , Paul F. Fortier , Kang-Wook Lee , Jae-Woong Nah , Soojae Park , Robert L. Toutant , Alain A. Warren
发明人： Pascal P. Blais , Paul F. Fortier , Kang-Wook Lee , Jae-Woong Nah , Soojae Park , Robert L. Toutant , Alain A. Warren
IPC分类号： B23K37/04 , B23K31/00
CPC分类号： B23K1/0016 , H01L21/563 , H01L24/75 , H01L24/81 , H01L2224/13099 , H01L2224/131 , H01L2224/73204 , H01L2224/75704 , H01L2224/75985 , H01L2224/81005 , H01L2224/81191 , H01L2224/81815 , H01L2224/8191 , H01L2924/01006 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01076 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/10253 , H01L2924/15787 , H01L2924/3511 , H01L2924/01026 , H01L2924/00
摘要： A method and apparatus for making chip assemblies is disclosed that prevent or reduce the cracking and delamination of ultra low-k dielectrics in the back-end-of-line in Si chips that can occur during the chip assembly process. The method and apparatus apply pressure to the top and bottom surfaces of a substrate during the chip bonding process so that the bending and warping of the assembled modules are reduced. The reduced bending and warping prevent or reduce the cracking and delamination of ultra low-k dielectrics.
摘要翻译：公开了一种用于制造芯片组件的方法和装置，其防止或减少在芯片组装过程中可能发生的Si芯片中后端的超低k电介质的开裂和分层。该方法和装置在芯片接合过程期间对基板的顶表面和底表面施加压力，使得组装的模块的弯曲和翘曲减小。减少弯曲和翘曲防止或减少超低k电介质的开裂和分层。

9. 发明授权

US09393633B2 Method of joining a chip on a substrate 有权
标题翻译：将芯片连接在基板上的方法
公开(公告)号：US09393633B2
公开(公告)日：2016-07-19
申请号：US12551960
申请日：2009-09-01
申请人： Pascal P Blais , Paul F Fortier , Kang-Wook Lee , Jae-Woong Nah , Soojae Park , Robert L Toutant , Alain A Warren
发明人： Pascal P Blais , Paul F Fortier , Kang-Wook Lee , Jae-Woong Nah , Soojae Park , Robert L Toutant , Alain A Warren
IPC分类号： B23K20/00 , B23K1/00 , H01L21/56 , H01L23/00
CPC分类号： B23K1/0016 , H01L21/563 , H01L24/75 , H01L24/81 , H01L2224/13099 , H01L2224/131 , H01L2224/73204 , H01L2224/75704 , H01L2224/75985 , H01L2224/81005 , H01L2224/81191 , H01L2224/81815 , H01L2224/8191 , H01L2924/01006 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01076 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/10253 , H01L2924/15787 , H01L2924/3511 , H01L2924/01026 , H01L2924/00
摘要： A method and apparatus for making chip assemblies is disclosed that prevent or reduce the cracking and delamination of ultra low-k dielectrics in the back-end-of-line in Si chips that can occur during the chip assembly process. The method and apparatus apply pressure to the top and bottom surfaces of a substrate during the chip bonding process so that the bending and warping of the assembled modules are reduced. The reduced bending and warping prevent or reduce the cracking and delamination of ultra low-k dielectrics.
摘要翻译：公开了一种用于制造芯片组件的方法和装置，其防止或减少在芯片组装过程中可能发生的Si芯片中后端的超低k电介质的开裂和分层。该方法和装置在芯片接合过程期间对基板的顶表面和底表面施加压力，使得组装的模块的弯曲和翘曲减小。减少弯曲和翘曲防止或减少超低k电介质的开裂和分层。

10. 发明授权

US08877566B2 Curvilinear heat spreader/lid with improved heat dissipation 有权
标题翻译：曲线散热器/盖具有改善的散热
公开(公告)号：US08877566B2
公开(公告)日：2014-11-04
申请号：US13586421
申请日：2012-08-15
申请人： Michael A. Gaynes , Maurice McGlashan-Powell , Soojae Park , Edward J. Yarmchuk
发明人： Michael A. Gaynes , Maurice McGlashan-Powell , Soojae Park , Edward J. Yarmchuk
IPC分类号： H01L21/00 , H01L23/42
CPC分类号： H01L23/42 , H01L2224/05573 , H01L2224/16 , H01L2224/73253 , H01L2924/10253 , H01L2924/3511 , H01L2924/00
摘要： A heat spreader or lid for a microelectronic package, in which the heat spreader has an underside surface that includes at least one curvilinear contour, in which the curvilinear contour is selected from at least one positive or protruding curvilinear feature, at least one negative or recessed curvilinear feature, and a combination thereof. A microelectronic package that includes the heat spreader/lid, in which there is improved heat dissipation or reduced mechanical stress in an interface between the heat spreader/lid and a circuit chip.
摘要翻译：一种用于微电子封装的散热器或盖，其中散热器具有包括至少一个曲线轮廓的下表面，其中曲线轮廓选自至少一个正或突出的曲线特征，至少一个负或凹入曲线特征及其组合。包括散热器/盖的微电子封装，其中在散热器/盖和电路芯片之间的界面中改善了散热或降低了机械应力。

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