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    • 8. 发明授权
    • Frequency-agile strobe window generation
    • 频敏捷频闪窗生成
    • US08824224B2
    • 2014-09-02
    • US13545255
    • 2012-07-10
    • Frederick A. WareBrian S. LeibowitzEly Tsern
    • Frederick A. WareBrian S. LeibowitzEly Tsern
    • G11C19/00
    • G11C29/023G06F13/1689G11C7/1066G11C29/022G11C29/028H03K5/135
    • The disclosed embodiments relate to components of a memory system that support frequency-agile strobe enable window generation during read accesses. In specific embodiments, this memory system contains a memory controller which includes a timing circuit to synchronize a timing-enable signal with a timing signal returned from a read path, wherein the timing signal includes a delay from the read path. In some embodiments, the timing circuit further comprises two calibration loops. The first calibration loop tracks the timing-enable signal with respect to a cycle-dependent delay in the delay, wherein the cycle-dependent delay depends on a frequency of the strobe signal. The second calibration loop tracks the timing-enable signal with respect to a cycle-independent delay in the delay, wherein the cycle-independent delay does not depend on the frequency of the strobe signal. In some embodiments, the first calibration loop and the second calibration loop are cascaded.
    • 所公开的实施例涉及在读取访问期间支持频率敏捷选通使能窗口生成的存储器系统的组件。 在具体实施例中,该存储器系统包括存储器控制器,其包括定时电路,以使定时使能信号与从读取路径返回的定时信号同步,其中定时信号包括来自读取路径的延迟。 在一些实施例中,定时电路还包括两个校准回路。 第一校准环路相对于延迟中的与周期相关的延迟跟踪定时使能信号,其中周期相关延迟取决于选通信号的频率。 第二校准环路相对于延迟中的与周期无关的延迟来跟踪定时使能信号,其中周期无关延迟不依赖于选通信号的频率。 在一些实施例中,级联第一校准回路和第二校准回路。