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1. 发明申请

US20060227620A1 Non-Volatile Memory Cells Utilizing Substrate Trenches 有权
标题翻译：非易失性记忆单元利用基底沟槽
公开(公告)号：US20060227620A1
公开(公告)日：2006-10-12
申请号：US11423121
申请日：2006-06-08
申请人： Eliyahou Harari , Jack Yuan , George Samachisa , Henry Chien
发明人： Eliyahou Harari , Jack Yuan , George Samachisa , Henry Chien
IPC分类号： G11C11/34 , G11C16/06
CPC分类号： H01L27/11521 , G11C16/0416 , H01L27/115 , H01L27/11553
摘要： Several embodiments of flash EEPROM split-channel cell arrays are described that position the channels of cell select transistors along sidewalls of trenches in the substrate, thereby reducing the cell area. Select transistor gates are formed as part of the word lines and extend downward into the trenches with capacitive coupling between the trench sidewall channel portion and the select gate. In one embodiment, trenches are formed between every other floating gate along a row, the two trench sidewalls providing the select transistor channels for adjacent cells, and a common source/drain diffusion is positioned at the bottom of the trench. A third gate provides either erase or steering capabilities. In another embodiment, trenches are formed between every floating gate along a row, a source/drain diffusion extending along the bottom of the trench and upwards along one side with the opposite side of the trench being the select transistor channel for a cell. In another embodiment, select transistor gates of dual floating gate memory cells are extended into trenches or recesses in the substrate in order to lengthen the select transistor channel as the surface dimensions of the cell are being decreased. Techniques for manufacturing such flash EEPROM split-channel cell arrays are also included.
摘要翻译：描述了闪存EEPROM分离通道单元阵列的几个实施例，其将单元选择晶体管的通道定位在衬底中的沟槽的侧壁，从而减小单元面积。选择晶体管栅极形成为字线的一部分，并且通过沟槽侧壁沟道部分和选择栅极之间的电容耦合向下延伸到沟槽中。在一个实施例中，在沿着一行的每隔一个浮置栅极之间形成沟槽，两个沟槽侧壁为相邻电池提供选择晶体管沟道，并且公共源极/漏极扩散部位于沟槽的底部。第三个门提供擦除或转向功能。在另一个实施例中，在沿着一排的每个浮置栅极之间形成沟槽，沿沟槽的底部延伸的源极/漏极扩散器和沿着一侧的向上并且沟槽的相对侧为用于电池的选择晶体管沟道。在另一个实施例中，双浮置栅极存储器单元的选择晶体管栅极延伸到衬底中的沟槽或凹槽中，以便随着单元的表面尺寸减小而延长选择晶体管沟道。还包括用于制造这种快速EEPROM分离通道单元阵列的技术。

2. 发明申请

US20080119026A1 Multi-State Non-Volatile Integrated Circuit Memory Systems that Employ Dielectric Storage Elements 有权
标题翻译：采用介质存储元件的多状态非易失性集成电路存储器系统
公开(公告)号：US20080119026A1
公开(公告)日：2008-05-22
申请号：US12020296
申请日：2008-01-25
申请人： Eliyahou Harari , George Samachisa , Jack Yuan , Daniel Guternam
发明人： Eliyahou Harari , George Samachisa , Jack Yuan , Daniel Guternam
IPC分类号： H01L21/8246
CPC分类号： H01L27/11568 , B82Y10/00 , G11C11/5671 , G11C16/0466 , G11C16/0475 , G11C16/0483 , G11C16/0491 , G11C2216/06 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/4234 , H01L29/7923 , Y10S438/947
摘要： Non-volatile memory cells store a level of charge corresponding to the data being stored in a dielectric material storage element that is sandwiched between a control gate and the semiconductor substrate surface over channel regions of the memory cells. More than two memory states are provided by one of more than two levels of charge being stored in a common region of the dielectric material. More than one such common region may be included in each cell. In one form, two such regions are provided adjacent source and drain diffusions in a cell that also includes a select transistor positioned between them. In another form, NAND arrays of strings of memory cells store charge in regions of a dielectric layer sandwiched between word lines and the semiconductor substrate.
摘要翻译：非易失性存储单元存储对应于存储在存储单元的沟道区上夹在控制栅极和半导体衬底表面之间的介电材料存储元件中的数据的电荷水平。通过存储在电介质材料的公共区域中的多于两个的电荷中的一个来提供两个以上的记忆状态。每个单元中可以包括多于一个这样的共同区域。在一种形式中，在单元中邻近的源和漏扩散设置了两个这样的区域，该单元还包括位于它们之间的选择晶体管。在另一种形式中，存储单元串的NAND阵列在夹在字线和半导体衬底之间的电介质层的区域中存储电荷。

3. 发明申请

US20080116509A1 Multi-State Non-Volatile Integrated Circuit Memory Systems that Employ Dielectric Storage Elements 有权
公开(公告)号：US20080116509A1
公开(公告)日：2008-05-22
申请号：US12020266
申请日：2008-01-25
申请人： Eliyahou Harari , George Samachisa , Jack Yuan , Daniel Guterman
发明人： Eliyahou Harari , George Samachisa , Jack Yuan , Daniel Guterman
IPC分类号： H01L29/792
CPC分类号： H01L27/11568 , B82Y10/00 , G11C11/5671 , G11C16/0466 , G11C16/0475 , G11C16/0483 , G11C16/0491 , G11C2216/06 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/4234 , H01L29/7923 , Y10S438/947
摘要： Non-volatile memory cells store a level of charge corresponding to the data being stored in a dielectric material storage element that is sandwiched between a control gate and the semiconductor substrate surface over channel regions of the memory cells. More than two memory states are provided by one of more than two levels of charge being stored in a common region of the dielectric material. More than one such common region may be included in each cell. In one form, two such regions are provided adjacent source and drain diffusions in a cell that also includes a select transistor positioned between them. In another form, NAND arrays of strings of memory cells store charge in regions of a dielectric layer sandwiched between word lines and the semiconductor substrate.

4. 发明申请

US20050157551A1 Multi-state non-volatile integrated circuit memory systems that employ dielectric storage elements 有权
公开(公告)号：US20050157551A1
公开(公告)日：2005-07-21
申请号：US11075427
申请日：2005-03-07
申请人： Eliyahou Harari , George Samachisa , Jack Yuan , Daniel Guterman
发明人： Eliyahou Harari , George Samachisa , Jack Yuan , Daniel Guterman
IPC分类号： G11C11/56 , G11C16/04 , H01L21/8246 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11568 , B82Y10/00 , G11C11/5671 , G11C16/0466 , G11C16/0475 , G11C16/0483 , G11C16/0491 , G11C2216/06 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/4234 , H01L29/7923 , Y10S438/947
摘要： Non-volatile memory cells store a level of charge corresponding to the data being stored in a dielectric material storage element that is sandwiched between a control gate and the semiconductor substrate surface over channel regions of the memory cells. More than two memory states are provided by one of more than two levels of charge being stored in a common region of the dielectric material. More than one such common region may be included in each cell. In one form, two such regions are provided adjacent source and drain diffusions in a cell that also includes a select transistor positioned between them. In another form, NAND arrays of strings of memory cells store charge in regions of a dielectric layer sandwiched between word lines and the semiconductor substrate.

5. 发明申请

US20070161191A1 Scalable Self-Aligned Dual Floating Gate Memory Cell Array And Methods Of Forming The Array 有权
标题翻译：可扩展自对准双浮动存储单元阵列和阵列形成方法
公开(公告)号：US20070161191A1
公开(公告)日：2007-07-12
申请号：US11689775
申请日：2007-03-22
申请人： Jack Yuan , Eliyahou Harari , Yupin Fong , George Samachisa
发明人： Jack Yuan , Eliyahou Harari , Yupin Fong , George Samachisa
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115 , H01L27/11531 , H01L27/11548 , H01L29/42328 , H01L29/7887
摘要： An integrated non-volatile memory circuit is formed by first growing a thin dielectric layer on a semiconductor substrate surface, followed by depositing a layer of conductive material such as doped polysilicon on this dielectric layer, the conductive material then being separated into rows and columns of individual floating gates. Cell source and drain diffusions in the substrate are continuously elongated across the rows. Field dielectric deposited between the rows of floating gates provides electrical isolation between the rows. Shallow trenches may be included between rows without interrupting the conductivity of the diffusions along their lengths. A deep dielectric filled trench is formed in the substrate between the array and peripheral circuits as electrical isolation. Various techniques are included that increase the field coupling area between the floating gates and a control gate. Other techniques increase the thickness of dielectric between control gates in order to decrease the field coupling between them.
摘要翻译：通过首先在半导体衬底表面上生长薄的电介质层，然后在该电介质层上沉积诸如掺杂多晶硅的导电材料层，然后将导电材料分离成行和列，形成集成的非易失性存储器电路个别浮动门。衬底中的电荷源和漏极扩散在整个行中连续延伸。沉积在浮动栅极行之间的场电介质在行之间提供电隔离。可以在行之间包括浅沟槽，而不会中断沿其长度的扩散的导电性。在阵列和外围电路之间的衬底中形成深电介质填充沟槽作为电隔离。包括增加浮动栅极和控制栅极之间的场耦合区域的各种技术。其他技术增加了控制栅之间的电介质厚度，以减小它们之间的场耦合。

6. 发明申请

US20050201154A1 Scalable self-aligned dual floating gate memory cell array and methods of forming the array 有权
标题翻译：可扩展自对准双浮栅存储单元阵列和形成阵列的方法
公开(公告)号：US20050201154A1
公开(公告)日：2005-09-15
申请号：US11111129
申请日：2005-04-20
申请人： Jack Yuan , Eliyahou Harari , Yupin Fong , George Samachisa
发明人： Jack Yuan , Eliyahou Harari , Yupin Fong , George Samachisa
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , H01L21/336 , G11C11/34 , G11C16/04
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115 , H01L27/11531 , H01L27/11548 , H01L29/42328 , H01L29/7887
摘要： An integrated non-volatile memory circuit is formed by first growing a thin dielectric layer on a semiconductor substrate surface, followed by depositing a layer of conductive material such as doped polysilicon on this dielectric layer, the conductive material then being separated into rows and columns of individual floating gates. Cell source and drain diffusions in the substrate are continuously-elongated across the rows. Field dielectric deposited between the rows of floating gates provides electrical isolation between the rows. Shallow trenches may be included between rows without interrupting the conductivity of the diffusions along their lengths. A deep dielectric filled trench is formed in the substrate between the array and peripheral circuits as electrical isolation. Various techniques are included that increase the field coupling area between the floating gates and a control gate. Other techniques increase the thickness of dielectric between control gates in order to decrease the field coupling between them.
摘要翻译：通过首先在半导体衬底表面上生长薄的电介质层，然后在该电介质层上沉积诸如掺杂多晶硅的导电材料层，然后将导电材料分离成行和列，形成集成的非易失性存储器电路个别浮动门。衬底中的电荷源和漏极扩散在整个行上连续伸长。沉积在浮动栅极行之间的场电介质在行之间提供电隔离。可以在行之间包括浅沟槽，而不会中断沿其长度的扩散的导电性。在阵列和外围电路之间的衬底中形成深电介质填充沟槽作为电隔离。包括增加浮动栅极和控制栅极之间的场耦合区域的各种技术。其他技术增加了控制栅之间的电介质厚度，以减小它们之间的场耦合。

7. 发明申请

US20050180210A1 Multi-state non-volatile integrated circuit memory systems that employ dielectric storage elements 有权
公开(公告)号：US20050180210A1
公开(公告)日：2005-08-18
申请号：US11075423
申请日：2005-03-07
申请人： Eliyahou Harari , George Samachisa , Jack Yuan , Daniel Guterman
发明人： Eliyahou Harari , George Samachisa , Jack Yuan , Daniel Guterman
IPC分类号： G11C11/56 , G11C16/04 , H01L21/8246 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11568 , B82Y10/00 , G11C11/5671 , G11C16/0466 , G11C16/0475 , G11C16/0483 , G11C16/0491 , G11C2216/06 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/4234 , H01L29/7923 , Y10S438/947
摘要： Non-volatile memory cells store a level of charge corresponding to the data being stored in a dielectric material storage element that is sandwiched between a control gate and the semiconductor substrate surface over channel regions of the memory cells. More than two memory states are provided by one of more than two levels of charge being stored in a common region of the dielectric material. More than one such common region may be included in each cell. In one form, two such regions are provided adjacent source and drain diffusions in a cell that also includes a select transistor positioned between them. In another form, NAND arrays of strings of memory cells store charge in regions of a dielectric layer sandwiched between word lines and the semiconductor substrate.

8. 发明授权

US07491999B2 Non-volatile memory cells utilizing substrate trenches 有权
标题翻译：利用衬底沟槽的非易失性存储单元
公开(公告)号：US07491999B2
公开(公告)日：2009-02-17
申请号：US11423121
申请日：2006-06-08
申请人： Eliyahou Harari , Jack H. Yuan , George Samachisa , Henry Chien
发明人： Eliyahou Harari , Jack H. Yuan , George Samachisa , Henry Chien
IPC分类号： H01L29/72
CPC分类号： H01L27/11521 , G11C16/0416 , H01L27/115 , H01L27/11553
摘要： Several embodiments of flash EEPROM split-channel cell arrays are described that position the channels of cell select transistors along sidewalls of trenches in the substrate, thereby reducing the cell area. Select transistor gates are formed as part of the word lines and extend downward into the trenches with capacitive coupling between the trench sidewall channel portion and the select gate. In one embodiment, trenches are formed between every other floating gate along a row, the two trench sidewalls providing the select transistor channels for adjacent cells, and a common source/drain diffusion is positioned at the bottom of the trench. A third gate provides either erase or steering capabilities. In another embodiment, trenches are formed between every floating gate along a row, a source/drain diffusion extending along the bottom of the trench and upwards along one side with the opposite side of the trench being the select transistor channel for a cell. In another embodiment, select transistor gates of dual floating gate memory cells are extended into trenches or recesses in the substrate in order to lengthen the select transistor channel as the surface dimensions of the cell are being decreased. Techniques for manufacturing such flash EEPROM split-channel cell arrays are also included.
摘要翻译：描述了闪存EEPROM分离通道单元阵列的几个实施例，其将单元选择晶体管的通道定位在衬底中的沟槽的侧壁，从而减小单元面积。选择晶体管栅极形成为字线的一部分，并且通过沟槽侧壁沟道部分和选择栅极之间的电容耦合向下延伸到沟槽中。在一个实施例中，在沿着一行的每隔一个浮置栅极之间形成沟槽，两个沟槽侧壁为相邻电池提供选择晶体管沟道，并且公共源极/漏极扩散部位于沟槽的底部。第三个门提供擦除或转向功能。在另一个实施例中，在沿着一排的每个浮置栅极之间形成沟槽，沿沟槽的底部延伸的源极/漏极扩散器和沿着一侧的向上并且沟槽的相对侧为用于电池的选择晶体管沟道。在另一个实施例中，双浮置栅极存储器单元的选择晶体管栅极延伸到衬底中的沟槽或凹槽中，以便随着单元的表面尺寸减小而延长选择晶体管沟道。还包括用于制造这种快速EEPROM分离通道单元阵列的技术。

9. 发明授权

US07087951B2 Non-volatile memory cells utilizing substrate trenches 有权
公开(公告)号：US07087951B2
公开(公告)日：2006-08-08
申请号：US10848242
申请日：2004-05-17
申请人： Eliyahou Harari , Jack H. Yuan , George Samachisa , Henry Chien
发明人： Eliyahou Harari , Jack H. Yuan , George Samachisa , Henry Chien
IPC分类号： H01L29/76
CPC分类号： H01L27/11521 , G11C16/0416 , H01L27/115 , H01L27/11553
摘要： Several embodiments of flash EEPROM split-channel cell arrays are described that position the channels of cell select transistors along sidewalls of trenches in the substrate, thereby reducing the cell area. Select transistor gates are formed as part of the word lines and extend downward into the trenches with capacitive coupling between the trench sidewall channel portion and the select gate. In one embodiment, trenches are formed between every other floating gate along a row, the two trench sidewalls providing the select transistor channels for adjacent cells, and a common source/drain diffusion is positioned at the bottom of the trench. A third gate provides either erase or steering capabilities. In another embodiment, trenches are formed between every floating gate along a row, a source/drain diffusion extending along the bottom of the trench and upwards along one side with the opposite side of the trench being the select transistor channel for a cell. In another embodiment, select transistor gates of dual floating gate memory cells are extended into trenches or recesses in the substrate in order to lengthen the select transistor channel as the surface dimensions of the cell are being decreased. Techniques for manufacturing such flash EEPROM split-channel cell arrays are also included.

10. 发明授权

US06936887B2 Non-volatile memory cells utilizing substrate trenches 有权
标题翻译：利用衬底沟槽的非易失性存储单元
公开(公告)号：US06936887B2
公开(公告)日：2005-08-30
申请号：US09925134
申请日：2001-08-08
申请人： Eliyahou Harari , Jack H. Yuan , George Samachisa , Henry Chien
发明人： Eliyahou Harari , Jack H. Yuan , George Samachisa , Henry Chien
IPC分类号： H01L27/10 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11521 , G11C16/0416 , H01L27/115 , H01L27/11553
摘要： Several embodiments of flash EEPROM split-channel cell arrays are described that position the channels of cell select transistors along sidewalls of trenches in the substrate, thereby reducing the cell area. Select transistor gates are formed as part of the word lines and extend downward into the trenches with capacitive coupling between the trench sidewall channel portion and the select gate. In one embodiment, trenches are formed between every other floating gate along a row, the two trench sidewalls providing the select transistor channels for adjacent cells, and a common source/drain diffusion is positioned at the bottom of the trench. A third gate provides either erase or steering capabilities. In another embodiment, trenches are formed between every floating gate along a row, a source/drain diffusion extending along the bottom of the trench and upwards along one side with the opposite side of the trench being the select transistor channel for a cell. In another embodiment, select transistor gates of dual floating gate memory cells are extended into trenches or recesses in the substrate in order to lengthen the select transistor channel as the surface dimensions of the cell are being decreased. Techniques for manufacturing such flash EEPROM split-channel cell arrays are also included.
摘要翻译：描述了闪存EEPROM分离通道单元阵列的几个实施例，其将单元选择晶体管的通道定位在衬底中的沟槽的侧壁，从而减小单元面积。选择晶体管栅极形成为字线的一部分，并且通过沟槽侧壁沟道部分和选择栅极之间的电容耦合向下延伸到沟槽中。在一个实施例中，在沿着一行的每隔一个浮置栅极之间形成沟槽，两个沟槽侧壁为相邻电池提供选择晶体管沟道，并且公共源极/漏极扩散部位于沟槽的底部。第三个门提供擦除或转向功能。在另一个实施例中，在沿着一排的每个浮置栅极之间形成沟槽，沿沟槽的底部延伸的源极/漏极扩散器和沿着一侧的向上并且沟槽的相对侧为用于电池的选择晶体管沟道。在另一个实施例中，双浮置栅极存储器单元的选择晶体管栅极延伸到衬底中的沟槽或凹槽中，以便随着单元的表面尺寸减小而延长选择晶体管沟道。还包括用于制造这种快速EEPROM分离通道单元阵列的技术。

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