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1. 发明授权

US08478907B1 Network interface device serving multiple host operating systems 失效
标题翻译：网络接口设备服务于多个主机操作系统
公开(公告)号：US08478907B1
公开(公告)日：2013-07-02
申请号：US11416717
申请日：2006-05-03
申请人： Eliezer Aloni , Kobby Carmona , Shay Mizrachi , Rafi Shalom , Merav Sicron , Dov Hirshfeld , Amit Oren , Caitlin Bestler , Uri Tal , Uri Elzur , Kan (Frankie) Fan , Scott McDaniel
发明人： Eliezer Aloni , Kobby Carmona , Shay Mizrachi , Rafi Shalom , Merav Sicron , Dov Hirshfeld , Amit Oren , Caitlin Bestler , Uri Tal , Uri Elzur , Kan (Frankie) Fan , Scott McDaniel
IPC分类号： G03F15/16 , G03F15/177 , G03F3/00
CPC分类号： G06F13/128 , Y02D10/14
摘要： A network interface device for use with a host computer that includes a host processor and a memory, and which is configured to concurrently run a master operating system and at least one virtual operating system. The device includes a bus interface that communicates over a bus with the host processor and the memory, and a network interface, which is coupled to send and receive data packets carrying data over a packet network. A protocol processor is coupled between the bus interface and the network interface so as to convey the data between the network interface and the memory while performing protocol processing on the data packets under instructions from the at least one virtual operating system, while bypassing the master operating system.
摘要翻译：一种用于与主计算机一起使用的网络接口设备，其包括主机处理器和存储器，并且被配置为并行运行主操作系统和至少一个虚拟操作系统。该设备包括通过总线与主机处理器和存储器进行通信的总线接口，以及耦合以通过分组网络发送和接收承载数据的数据分组的网络接口。协议处理器耦合在总线接口和网络接口之间，以便在来自至少一个虚拟操作系统的指令下对数据分组执行协议处理时，在网络接口和存储器之间传送数据，同时绕过主操作系统。

2. 发明授权

US07835380B1 Multi-port network interface device with shared processing resources 有权
标题翻译：具有共享处理资源的多端口网络接口设备
公开(公告)号：US07835380B1
公开(公告)日：2010-11-16
申请号：US11416677
申请日：2006-05-03
申请人： Eliezer Aloni , Kobby Carmona , Shay Mizrachi , Rafi Shalom , Merav Sicron , Dov Hirshfeld , Amit Oren , Caitlin Bestler , Uri Tal , Steven B. Lindsay , Kan (Frankie) Fan , Hav Khauv
发明人： Eliezer Aloni , Kobby Carmona , Shay Mizrachi , Rafi Shalom , Merav Sicron , Dov Hirshfeld , Amit Oren , Caitlin Bestler , Uri Tal , Steven B. Lindsay , Kan (Frankie) Fan , Hav Khauv
IPC分类号： H04L12/28 , H04L12/413 , G06F15/16 , G06F15/173
CPC分类号： H04L12/40032 , H04L12/413
摘要： A network interface device includes a bus interface that communicates over a bus with a host processor and memory, and a network interface, including at least first and second physical ports, which are coupled to send and receive data packets carrying data over a packet network. A protocol processor includes a single transmit processing pipeline and a single receive processing pipeline, which are coupled between the bus interface and the network interface so as to convey the data between both of the first and second physical ports of the network interface and the memory via the bus interface while performing protocol offload processing on the data packets.
摘要翻译：网络接口设备包括通过总线与主机处理器和存储器进行通信的总线接口，以及包括至少第一和第二物理端口的网络接口，其耦合以通过分组网络发送和接收承载数据的数据分组。协议处理器包括单个发送处理流水线和单个接收处理流水线，其连接在总线接口和网络接口之间，以便在网络接口的第一和第二物理端口与存储器之间传送数据总线接口，同时对数据包执行协议卸载处理。

3. 发明授权

US07826470B1 Network interface device with flow-oriented bus interface 失效
标题翻译：网络接口设备，具有流向总线接口
公开(公告)号：US07826470B1
公开(公告)日：2010-11-02
申请号：US11416817
申请日：2006-05-03
申请人： Eliezer Aloni , Kobby Carmona , Shay Mizrachi , Rafi Shalom , Merav Sicron , Dov Hirshfeld , Amit Oren , Caitlin Bestler , Uri Tal
发明人： Eliezer Aloni , Kobby Carmona , Shay Mizrachi , Rafi Shalom , Merav Sicron , Dov Hirshfeld , Amit Oren , Caitlin Bestler , Uri Tal
IPC分类号： H02L12/28
CPC分类号： H04L49/9063 , H04L49/90
摘要： A network interface device includes a bus interface that communicates over a bus with a host processor and memory, and a network interface that sends and receive data packets carrying data over a packet network. A protocol processor conveys the data between the network interface and the memory via the bus interface while performing protocol offload processing on the data packets in accordance with multiple different application flows. The bus interface queues the data for transmission over the bus in a plurality of queues that are respectively assigned to the different application flows, and transmits the data over the bus according to the queues.
摘要翻译：网络接口设备包括通过总线与主机处理器和存储器通信的总线接口，以及通过分组网络发送和接收承载数据的数据分组的网络接口。协议处理器通过总线接口在网络接口和存储器之间传送数据，同时根据多个不同的应用程序流对数据包执行协议卸载处理。总线接口对数据进行排队，以便在分配给不同应用流的多个队列中通过总线传输，并根据队列通过总线发送数据。

4. 发明授权

US07688838B1 Efficient handling of work requests in a network interface device 有权
标题翻译：在网络接口设备中高效地处理工作请求
公开(公告)号：US07688838B1
公开(公告)日：2010-03-30
申请号：US11416919
申请日：2006-05-03
申请人： Eliezer Aloni , Kobby Carmona , Shay Mizrachi , Rafi Shalom , Caitlin Bestler , Merav Sicron , Dov Hirshfeld , Amit Oren , Uri Tal
发明人： Eliezer Aloni , Kobby Carmona , Shay Mizrachi , Rafi Shalom , Caitlin Bestler , Merav Sicron , Dov Hirshfeld , Amit Oren , Uri Tal
IPC分类号： H04L12/28
CPC分类号： G06F13/128 , G06F13/385 , Y02D10/14 , Y02D10/151
摘要： A method for communication includes inputting from a host processor to a network interface device a sequence of work requests indicative of operations to be carried out by the network interface device with respect to a plurality of the connections. The device looks ahead through the sequence in order to identify at least first and second operations that are to be carried out with respect to one of the connections in response to first and second work requests, respectively, wherein the second work request does not immediately follow the first work request in the sequence. The device loads the context data for the one of the connections from a host memory into a context cache, and performs at least the first and second operations sequentially while the context data are held in the cache.
摘要翻译：一种用于通信的方法包括从主机处理器向网络接口设备输入指示由网络接口设备相对于多个连接执行的操作的工作请求序列。所述设备通过所述序列向前看，以便分别响应于第一和第二工作请求来识别要相对于一个连接执行的至少第一和第二操作，其中第二工作请求不立即跟随序列中的第一个工作请求。该设备将来自主机存储器的一个连接的上下文数据加载到上下文高速缓存中，并且在将上下文数据保存在高速缓存中时，至少执行第一和第二操作。

5. 发明授权

US08155135B2 Network interface device with flow-oriented bus interface 有权
标题翻译：网络接口设备，具有流向总线接口
公开(公告)号：US08155135B2
公开(公告)日：2012-04-10
申请号：US12857325
申请日：2010-08-16
申请人： Eliezer Aloni , Kobby Carmona , Shay Mizrachi , Rafi Shalom , Mcrav Sicron , Dov Hirshfeld , Amit Oren , Caitlin Bestler , Uri Tal
发明人： Eliezer Aloni , Kobby Carmona , Shay Mizrachi , Rafi Shalom , Mcrav Sicron , Dov Hirshfeld , Amit Oren , Caitlin Bestler , Uri Tal
IPC分类号： H04L12/28
CPC分类号： H04L49/9063 , H04L49/90
摘要： A network interface device includes a bus interface that communicates over a bus with a host processor and memory, and a network interface that sends and receive data packets carrying data over a packet network. A protocol processor conveys the data between the network interface and the memory via the bus interface while performing protocol offload processing on the data packets in accordance with multiple different application flows. The bus interface queues the data for transmission over the bus in a plurality of queues that are respectively assigned to the different application flows, and transmits the data over the bus according to the queues.
摘要翻译：网络接口设备包括通过总线与主机处理器和存储器通信的总线接口，以及通过分组网络发送和接收承载数据的数据分组的网络接口。协议处理器通过总线接口在网络接口和存储器之间传送数据，同时根据多个不同的应用程序流对数据包执行协议卸载处理。总线接口对数据进行排队，以便在分配给不同应用流的多个队列中通过总线传输，并根据队列通过总线发送数据。

6. 发明申请

US20100312941A1 NETWORK INTERFACE DEVICE WITH FLOW-ORIENTED BUS INTERFACE 有权
标题翻译：具有流向总线接口的网络接口设备
公开(公告)号：US20100312941A1
公开(公告)日：2010-12-09
申请号：US12857325
申请日：2010-08-16
申请人： Eliezer Aloni , Kobby Carmona , Shay Mizrachi , Rafi Shalom , Mcrav Sicron , Dov Hirshfeld , Amit Oren , Caitlin Bestler , Uri Tal
发明人： Eliezer Aloni , Kobby Carmona , Shay Mizrachi , Rafi Shalom , Mcrav Sicron , Dov Hirshfeld , Amit Oren , Caitlin Bestler , Uri Tal
IPC分类号： G06F13/36
CPC分类号： H04L49/9063 , H04L49/90
摘要： A network interface device includes a bus interface that communicates over a bus with a host processor and memory, and a network interface that sends and receive data packets carrying data over a packet network. A protocol processor conveys the data between the network interface and the memory via the bus interface while performing protocol offload processing on the data packets in accordance with multiple different application flows. The bus interface queues the data for transmission over the bus in a plurality of queues that are respectively assigned to the different application flows, and transmits the data over the bus according to the queues.
摘要翻译：网络接口设备包括通过总线与主机处理器和存储器通信的总线接口，以及通过分组网络发送和接收承载数据的数据分组的网络接口。协议处理器通过总线接口在网络接口和存储器之间传送数据，同时根据多个不同的应用程序流对数据包执行协议卸载处理。总线接口对数据进行排队，以便在分配给不同应用流的多个队列中通过总线传输，并根据队列通过总线发送数据。

7. 发明申请

US20080235484A1 Method and System for Host Memory Alignment 审中-公开
标题翻译：主机内存对齐方法和系统
公开(公告)号：US20080235484A1
公开(公告)日：2008-09-25
申请号：US12052878
申请日：2008-03-21
申请人： Uri Tal , Eliezer Aloni , Shay Mizrachi , Kobby Carmona
发明人： Uri Tal , Eliezer Aloni , Shay Mizrachi , Kobby Carmona
IPC分类号： G06F12/02
CPC分类号： G06F12/04 , G06F13/28
摘要： Certain aspects of a method and system for host memory alignment may include splitting a received read and/or write I/O request at a first of a plurality of memory cache line boundaries to generate a first portion of the received I/O request. A second portion of the received read and/or write I/O request may be split into a plurality of segments so that each of the plurality of segments is aligned with one or more of the plurality of memory cache line boundaries. A cost of memory bandwidth for accessing host memory may be minimized based on the splitting of the second portion of the received read and/or write I/O request.
摘要翻译：用于主机存储器对准的方法和系统的某些方面可以包括在多个存储器高速缓存行边界的第一个处拆分所接收的读取和/或写入I / O请求，以生成所接收的I / O请求的第一部分。所接收的读取和/或写入I / O请求的第二部分可以被分割成多个段，使得多个段中的每一个与多个存储器高速缓存行边界中的一个或多个对齐。基于接收到的读取和/或写入I / O请求的第二部分的分割，可以最小化用于访问主机存储器的存储器带宽的成本。

8. 发明申请

US20080091868A1 Method and System for Delayed Completion Coalescing 审中-公开
标题翻译：延迟完成合并的方法和系统
公开(公告)号：US20080091868A1
公开(公告)日：2008-04-17
申请号：US11873802
申请日：2007-10-17
申请人： Shay Mizrachi , Eliezer Aloni , Uri Tal
发明人： Shay Mizrachi , Eliezer Aloni , Uri Tal
IPC分类号： G06F13/24
CPC分类号： G06F13/24
摘要： Certain aspects of a method and system for delayed completion coalescing may be disclosed. Exemplary aspects of the method may include accumulating a plurality of bytes of incoming TCP segments in a host memory until a number of the plurality of bytes of incoming TCP segments reaches a threshold value. A completion queue entry (CQE) may be generated to a driver when the plurality of bytes of incoming TCP segments reaches the threshold value and the plurality of bytes of incoming TCP segments may be copied to a user application. The method may also include delaying in a driver, an update of a TCP receive window size until one of the incoming TCP segments corresponding to a particular sequence number is copied to the user application. The CQE may also be generated to the driver when at least one of the incoming TCP segments is received with a TCP PUSH bit SET and the TCP receive window size is greater than a particular window size value.
摘要翻译：可以公开用于延迟完成聚结的方法和系统的某些方面。方法的示例性方面可以包括在主机存储器中累积进入的TCP段的多个字节，直到输入TCP段的多个字节数达到阈值。当进入的TCP段的多个字节达到阈值并且多个字节的传入TCP片段可以被复制到用户应用时，可以向驱动器生成完成队列条目（CQE）。该方法还可以包括延迟驱动程序，TCP接收窗口大小的更新，直到对应于特定序列号的一个进入TCP段被复制到用户应用程序。当使用TCP PUSH位SET接收至少一个进入的TCP段时，也可以向驱动程序生成CQE，并且TCP接收窗口大小大于特定的窗口大小值。

9. 发明授权

US08751211B2 Simulation using parallel processors 有权
标题翻译：仿真使用并行处理器
公开(公告)号：US08751211B2
公开(公告)日：2014-06-10
申请号：US12810310
申请日：2009-03-25
申请人： Uri Tal , Shay Mizrachi , Tomer Ben-David
发明人： Uri Tal , Shay Mizrachi , Tomer Ben-David
IPC分类号： G06G7/62 , G06F17/50
CPC分类号： G06F17/5022 , G06F8/45 , G06F17/505
摘要： A method for design simulation includes partitioning a verification task of a design into a first plurality of atomic Processing Elements (PEs) having execution dependencies, each execution dependency specifying that a respective first PE is to be executed before a respective second PE. The method further includes computing an order for executing the PEs on a multiprocessor device, which includes a second plurality of processors operating in parallel and schedules the PEs for execution by the processors according to a built-in scheduling policy. The order induces concurrent execution of the PEs by different ones of the processors without violating the execution dependencies irrespective of the scheduling policy. The PEs are executed on the processors in accordance with the computed order and the scheduling policy, to produce a simulation result. A performance of the design is verified responsively to the simulation result.
摘要翻译：一种用于设计模拟的方法包括将设计的验证任务划分为具有执行依赖性的第一多个原子处理元件（PE），每个执行依赖性指定在相应的第二PE之前执行相应的第一PE。该方法还包括计算用于在多处理器设备上执行PE的顺序，该多处理器设备包括并行操作的第二多个处理器，并根据内置的调度策略调度PE以供处理器执行。该顺序引起不同处理器的PE的并发执行，而不违反执行依赖关系，而与调度策略无关。 PE根据计算的顺序和调度策略在处理器上执行，以产生模拟结果。响应于仿真结果验证设计的性能。

10. 发明申请

US20110191092A1 PARALLEL SIMULATION USING MULTIPLE CO-SIMULATORS 有权
标题翻译：使用多个共同模拟器的并行仿真
公开(公告)号：US20110191092A1
公开(公告)日：2011-08-04
申请号：US13084574
申请日：2011-04-12
申请人： Shay Mizrachi , Uri Tal , Tomer Ben-David , Ishay Geller , Ido Kasher
发明人： Shay Mizrachi , Uri Tal , Tomer Ben-David , Ishay Geller , Ido Kasher
IPC分类号： G06F17/50 , G06F9/46
CPC分类号： G06F9/4843 , G06F9/46 , G06F17/50 , G06F17/5036
摘要： A method includes accepting a simulation task for simulation by a simulator that controls multiple co-simulators. Each of the multiple co-simulators is assigned to execute one or more respective sub-tasks of the simulation task. The simulation task is executed by invoking each co-simulator to execute the respective assigned sub-tasks.
摘要翻译：一种方法包括接受用于由控制多个共模拟器的模拟器进行仿真的模拟任务。多个协同模拟器中的每一个被分配以执行模拟任务的一个或多个相应的子任务。通过调用每个协同仿真器来执行相应的分配的子任务来执行模拟任务。

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