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1. 发明授权

US5075241A Method of forming a recessed contact bipolar transistor and field effect device 失效
标题翻译：形成凹陷接触双极晶体管和场效应器件的方法
公开(公告)号：US5075241A
公开(公告)日：1991-12-24
申请号：US542294
申请日：1990-06-22
申请人： David B. Spratt , Robert L. Virkus , Robert H. Eklund , Eldon J. Zorinsky
发明人： David B. Spratt , Robert L. Virkus , Robert H. Eklund , Eldon J. Zorinsky
IPC分类号： H01L29/73
CPC分类号： H01L29/7317 , Y10S148/009
摘要： Disclosed is a scaled, self aligned, bipolar transistor and a method of fabrication which is compatible with MOSFET device structures. A transistor intrinsic base region is formed in the face of an isolated epitaxial region and polysilicon is deposited, patterned and etched to form emitter regions. An oxide cap and first sidewall oxide spacers are formed on the polysilicon emitters and the single crystal silicon is etched using the oxide covered emitters as a mask to form recessed regions in the epitaxial layer. The extrinsic base region is then formed adjacent at least one side of the base by implanting appropriate dopants into one of the recessed regions. A second sidewall oxide spacer is then formed on the vertical base emitter structure and a heavily doped collector contact region is formed by implanting appropriate dopants into another one of the recessed silicon regions. The collector contact region is self aligned to the second sidewall oxide spacer which prevents the contact of base and heavily doped collector. Finally, the oxide cap covering the upper emitter surfaces is removed and emitter, base and collector contact regions are silicided to reduce contact resistance.
摘要翻译：公开了一种缩放的自对准双极晶体管和与MOSFET器件结构兼容的制造方法。晶体管本征基极区形成在隔离的外延区域的表面，多晶硅沉积，图案化和蚀刻以形成发射极区域。在多晶硅发射体上形成氧化物盖和第一侧壁氧化物间隔物，并且使用氧化物覆盖的发射体作为掩模蚀刻单晶硅，以在外延层中形成凹陷区域。然后通过将适当的掺杂剂注入到一个凹陷区域中而形成在基底的至少一侧附近的非本征基区。然后在垂直基极发射器结构上形成第二侧壁氧化物间隔物，并且通过将适当的掺杂剂注入到另一个凹陷硅区域中来形成重掺杂的集电极接触区域。集电极接触区域与第二侧壁氧化物间隔物自对准，防止基极和重掺杂的集电极接触。最后，去除覆盖上部发射极表面的氧化物盖，并将发射极，基极和集电极接触区域硅化，以降低接触电阻。

2. 发明授权

US4897703A Recessed contact bipolar transistor and method 失效
标题翻译：嵌入式双极晶体管和方法
公开(公告)号：US4897703A
公开(公告)日：1990-01-30
申请号：US149785
申请日：1988-01-29
申请人： David B. Spratt , Robert L. Virkus , Robert H. Eklund , Eldon J. Zorinsky
发明人： David B. Spratt , Robert L. Virkus , Robert H. Eklund , Eldon J. Zorinsky
IPC分类号： H01L29/73
CPC分类号： H01L29/7317 , Y10S148/01
摘要： Disclosed is a scaled, self aligned, bipolar transistor and a method of fabrication which is compatible with MOSFET device structures. A transistor intrinsic base region is formed in the face of an isolated epitaxial region and polysilicon is deposited, patterned and etched to form emitter regions. An oxide cap and first sidewall oxide spacers are formed on the polysilicon emitters and the single crystal silicon is etched using the oxide covered emitters as a mask to form recessed regions in the epitaxial layer. The extrinsic base region is then formed adjacent at least one side of the base by implanting appropriate dopants into one of the recessed regions. A second sidewall oxide spacer is then formed on the vertical base emitter structure and a heavily doped collector contact region is formed by implanting appropriate dopants into another one of the recessed silicon regions. The collector contact region is self aligned to the second sidewall oxide spacer which prevents the contact of base and heavily doped collector. Finally, the oxide cap covering the upper emitter surfaces is removed and emitter, base and collector contact regions are silicided to reduce contact resistance.
摘要翻译：公开了一种缩放的自对准双极晶体管和与MOSFET器件结构兼容的制造方法。晶体管本征基极区形成在隔离的外延区域的表面，多晶硅沉积，图案化和蚀刻以形成发射极区域。在多晶硅发射体上形成氧化物盖和第一侧壁氧化物间隔物，并且使用氧化物覆盖的发射体作为掩模蚀刻单晶硅，以在外延层中形成凹陷区域。然后通过将适当的掺杂剂注入到一个凹陷区域中而形成在基底的至少一侧附近的非本征基区。然后在垂直基极发射器结构上形成第二侧壁氧化物间隔物，并且通过将适当的掺杂剂注入到另一个凹陷硅区域中来形成重掺杂的集电极接触区域。集电极接触区域与第二侧壁氧化物间隔物自对准，防止基极和重掺杂的集电极接触。最后，去除覆盖上部发射极表面的氧化物盖，并将发射极，基极和集电极接触区域硅化，以降低接触电阻。

3. 发明授权

US4810667A Dielectric isolation using isolated silicon by limited anodization of an N+ epitaxially defined sublayer in the presence of a diffusion under film layer 失效
标题翻译：通过在膜层下的扩散存在下，通过N +外延限定子层的有限阳极氧化，使用隔离硅的介质隔离
公开(公告)号：US4810667A
公开(公告)日：1989-03-07
申请号：US43510
申请日：1987-04-28
申请人： Eldon J. Zorinsky , David B. Spratt , Richard L. Yeakley
发明人： Eldon J. Zorinsky , David B. Spratt , Richard L. Yeakley
IPC分类号： H01L21/331 , H01L21/76 , H01L21/762 , H01L29/73 , H01L29/732 , H01L29/70
CPC分类号： H01L21/76264 , H01L21/7627 , H01L21/76283
摘要： The disclosure relates to a method of forming an isolated semiconductor, preferably of the vertical bipolar variety, wherein a porous highly doped semiconductor layer is oxidized and, with a trench containing silicon oxide therein, forms a region encasing a moderately doped epitaxial layer disposed beneath a lightly doped epitaxial layer. The vertical bipolar device is formed in the moderately doped and lightly doped layers with the highly doped epitaxially deposited layer, which is now a silicon oxide layer, forming a portion of the isolation. The anodization of the highly doped layer takes place using an anodizing acid at a temperature of from about 0 to about 10 degrees C.
摘要翻译：本公开涉及一种形成隔离半导体的方法，优选为垂直双极型，其中多孔高掺杂半导体层被氧化，并且其中含有氧化硅的沟槽形成包围中等掺杂外延层的区域轻掺杂的外延层。垂直双极器件在中等掺杂和轻掺杂层中形成，其中高度掺杂的外延沉积层现在是氧化硅层，形成隔离的一部分。高掺杂层的阳极氧化是在约0至约10℃的温度下使用阳极氧化酸进行的。

4. 发明授权

US4628591A Method for obtaining full oxide isolation of epitaxial islands in silicon utilizing selective oxidation of porous silicon 失效
标题翻译：利用多孔硅的选择性氧化获得硅中的外延岛全部氧化物分离的方法
公开(公告)号：US4628591A
公开(公告)日：1986-12-16
申请号：US666698
申请日：1984-10-31
申请人： Eldon J. Zorinsky , David B. Spratt
发明人： Eldon J. Zorinsky , David B. Spratt
IPC分类号： H01L21/205 , H01L21/306 , H01L21/762 , H01L21/76
CPC分类号： H01L21/762 , H01L21/306 , Y10S148/026 , Y10S148/05 , Y10S148/085
摘要： Full oxide isolation of epitaxial islands can be accomplished by oxidizing suitably porous silicon. The porous silicon can be created by anodizing highly doped n+ silicon in hydroflouric acid. Lesser doped epitaxial regions will not become porous and will become isolated islands suitable for the fabrication of semiconductor devices.
摘要翻译：外延岛的全氧化物隔离可以通过氧化合适的多孔硅来实现。可以通过在氢氟酸中阳极氧化高掺杂的n +硅来产生多孔硅。较小掺杂的外延区域将不会变得多孔，并且将成为适于制造半导体器件的隔离岛。

5. 发明授权

US4985744A Method for forming a recessed contact bipolar transistor and field effect transistor 失效
标题翻译：用于形成凹陷接触双极晶体管和场效应晶体管的方法
公开(公告)号：US4985744A
公开(公告)日：1991-01-15
申请号：US411208
申请日：1989-09-21
申请人： David B. Spratt , Robert L. Virkus , Robert H. Eklund , Eldon J. Zorinsky
发明人： David B. Spratt , Robert L. Virkus , Robert H. Eklund , Eldon J. Zorinsky
IPC分类号： H01L29/73
CPC分类号： H01L29/7317
摘要： Disclosed is a scaled, self aligned, bipolar transistor and a method of fabrication which is compatible with MOSFET device structures. A transistor intrinsic base region is formed in the face of an isolated epitaxial region and polysilicon is deposited, patterned and etched to form emitter regions. An oxide cap and first sidewall oxide spacers are formed on the polysilicon emitters and the single crystal silicon is etched using the oxide covered emitters as a mask to form recessed regions in the epitaxial layer. The extrinsic base region is then formed adjacent at least one side of the base by implanting appropriate dopants into one of the recessed regions. A second sidewall oxide spacer is then formed on the vertical base emitter structure and a heavily doped collector contact region is formed by implanting appropriate dopants into another one of the recessed silicon regions. The collector contact region is self aligned to the second sidewall oxide spacer which prevents the contact of base and heavily doped collector. Finally, the oxide cap covering the upper emitter surfaces is removed and emitter, base and collector contact regions are silicided to reduce contact resistance.
摘要翻译：公开了一种缩放的自对准双极晶体管和与MOSFET器件结构兼容的制造方法。晶体管本征基极区形成在隔离的外延区域的表面，多晶硅沉积，图案化和蚀刻以形成发射极区域。在多晶硅发射体上形成氧化物盖和第一侧壁氧化物间隔物，并且使用氧化物覆盖的发射体作为掩模蚀刻单晶硅，以在外延层中形成凹陷区域。然后通过将适当的掺杂剂注入到一个凹陷区域中而形成在基底的至少一侧附近的非本征基区。然后在垂直基极发射器结构上形成第二侧壁氧化物间隔物，并且通过将适当的掺杂剂注入到另一个凹陷硅区域中来形成重掺杂的集电极接触区域。集电极接触区域与第二侧壁氧化物间隔物自对准，防止基极和重掺杂的集电极接触。最后，去除覆盖上部发射极表面的氧化物盖，并将发射极，基极和集电极接触区域硅化，以降低接触电阻。

6. 发明授权

US4891103A Anadization system with remote voltage sensing and active feedback control capabilities 失效
标题翻译：具有远程电压感测和主动反馈控制功能的负载系统
公开(公告)号：US4891103A
公开(公告)日：1990-01-02
申请号：US235130
申请日：1988-08-23
申请人： Eldon J. Zorinsky , David B. Spratt
发明人： Eldon J. Zorinsky , David B. Spratt
IPC分类号： C25D11/32 , C25D21/12
CPC分类号： C25D21/12 , C25D11/32
摘要： The disclosure relates to a process station to precisely control the electrochemical anodization of specially prepared silicon substrates. Remotely placed voltage probes are utilized to monitor changes in the potential drop across the wafer as the anodization proceeds. As the available anodilizable area changes, the voltage drop across the wafer and hence the anodization current density is maintained at the desired value by the computer through the use of active feedback provided by these probes. Any desired anodization conditions can be programmed into the system using the system software, thereby adding an even greater degree of control over the process.
摘要翻译：本公开涉及精确地控制特别制备的硅衬底的电化学阳极氧化的工艺站。远程放置的电压探头用于监测阳极氧化进行时晶片上的电位降的变化。随着可用的阳极氧化面积的变化，晶片上的电压降以及阳极氧化电流密度由计算机通过使用由这些探针提供的主动反馈保持在期望的值。任何所需的阳极氧化条件可以使用系统软件编程到系统中，从而对该过程增加更大程度的控制。

7. 发明授权

US5316957A Method of forming a recessed contact bipolar transistor 失效
标题翻译：形成凹陷接触双极晶体管的方法
公开(公告)号：US5316957A
公开(公告)日：1994-05-31
申请号：US85676
申请日：1993-06-30
申请人： David B. Spratt , Robert L. Virkus , Robert H. Eklund , Eldon J. Zorinsky
发明人： David B. Spratt , Robert L. Virkus , Robert H. Eklund , Eldon J. Zorinsky
IPC分类号： H01L29/73 , H01L21/265
CPC分类号： H01L29/7317 , Y10S148/01
摘要： Disclosed is a scaled, self aligned, bipolar transistor and a method of fabrication which is compatible with MOSFET device structures. A transistor intrinsic base region is formed in the face of an isolated epitaxial region and polysilicon is deposited, patterned and etched to form emitter regions. An oxide cap and first sidewall oxide spacers are formed on the polysilicon emitters and the single crystal silicon is etched using the oxide covered emitters as a mask to form recessed regions in the epitaxial layer. The extrinsic base region is then formed adjacent at least one side of the base by implanting appropriate dopants into one of the recessed regions. A second sidewall oxide spacer is then formed on the vertical base emitter structure and a heavily doped collector contact region is formed by implanting appropriate dopants into another one of the recessed silicon regions. The collector contact region is self aligned to the second sidewall oxide spacer which prevents the contact of base and heavily doped collector. Finally, the oxide cap covering the upper emitter surfaces is removed and emitter, base and collector contact regions are silicided to reduce contact resistance.
摘要翻译：公开了一种缩放的自对准双极晶体管和与MOSFET器件结构兼容的制造方法。晶体管本征基极区形成在隔离的外延区域的表面，多晶硅沉积，图案化和蚀刻以形成发射极区域。在多晶硅发射体上形成氧化物盖和第一侧壁氧化物间隔物，并且使用氧化物覆盖的发射体作为掩模蚀刻单晶硅，以在外延层中形成凹陷区域。然后通过将适当的掺杂剂注入到一个凹陷区域中而形成在基底的至少一侧附近的非本征基区。然后在垂直基极发射器结构上形成第二侧壁氧化物间隔物，并且通过将适当的掺杂剂注入到另一个凹陷硅区域中来形成重掺杂的集电极接触区域。集电极接触区域与第二侧壁氧化物间隔物自对准，防止基极和重掺杂的集电极接触。最后，去除覆盖上部发射极表面的氧化物盖，并将发射极，基极和集电极接触区域硅化，以降低接触电阻。

8. 发明授权

US5019525A Method for forming a horizontal self-aligned transistor 失效
标题翻译：用于形成水平自对准晶体管的方法
公开(公告)号：US5019525A
公开(公告)日：1991-05-28
申请号：US548177
申请日：1990-07-05
申请人： Robert L. Virkus , David B. Spratt , Eldon J. Zorinsky
发明人： Robert L. Virkus , David B. Spratt , Eldon J. Zorinsky
IPC分类号： H01L21/225 , H01L21/285 , H01L21/331
CPC分类号： H01L29/6625 , H01L21/2257 , H01L21/28525 , Y10S148/15
摘要： A method for forming a self-aligned horizontal transistor includes the step of first defining a narrow base contact on an isolated N-tank (10) to define a first reference edge (41). A layer of sidewall oxide (40) is then disposed on the vertical wall of the base contact (34) to define a second reference edge (42). An emitter well (44) and a collector well (46) are then defined on either side of the contact with the vertical wall of the emitter well (44) aligned with the reference edge (42). A dopant material is then disposed adjacent the reference edge (42) and the dopant diffused into the substrate from a lateral direction to form a P-type base region (58) with a graded impurity profile. N-doped regions (64) and (66) are then formed in the emitter and collector wells to form the emitter and collector of the transistor.
摘要翻译：用于形成自对准水平晶体管的方法包括以下步骤：首先在隔离的N型罐（10）上限定窄基座接触以限定第一参考边缘（41）。然后将一层侧壁氧化物（40）设置在基部触点（34）的垂直壁上以限定第二参考边缘（42）。然后，在与基准边缘（42）对准的发射极（44）的垂直壁的触点的任一侧上限定发射极（44）和收集阱（46）。然后将掺杂剂材料邻近参考边缘（42）设置，并且掺杂剂从横向方向扩散到衬底中以形成具有渐变杂质分布的P型基极区（58）。然后在发射极和集电极阱中形成N掺杂区域（64）和（66），以形成晶体管的发射极和集电极。

9. 发明授权

US4982263A Anodizable strain layer for SOI semiconductor structures 失效
标题翻译：用于SOI半导体结构的可阳极氧化应变层
公开(公告)号：US4982263A
公开(公告)日：1991-01-01
申请号：US321612
申请日：1989-03-10
申请人： David B. Spratt , Eldon J. Zorinsky , Robert L. Virkus , Kenneth E. Bean , Richard L. Yeakley
发明人： David B. Spratt , Eldon J. Zorinsky , Robert L. Virkus , Kenneth E. Bean , Richard L. Yeakley
IPC分类号： H01L21/20 , H01L21/762
CPC分类号： H01L21/76264 , H01L21/02381 , H01L21/0245 , H01L21/02532 , H01L21/0262 , H01L21/7627 , H01L21/76283 , Y10S438/938 , Y10S438/96
摘要： A silicon on insulator semiconductor structure employs a strain layer fabricated of an electrically inactive material. The strain layer comprises silicon with a germanium additive to produce a sublayer exhibiting a low breakdown voltage and thus effective for selective anodization.
摘要翻译：绝缘体上硅半导体结构采用由电惰性材料制成的应变层。应变层包括具有锗添加剂的硅以产生显示低击穿电压的子层，因此对于选择性阳极氧化是有效的。

10. 发明授权

US4897698A Horizontal structure thin film transistor 失效
标题翻译：水平结构薄膜晶体管
公开(公告)号：US4897698A
公开(公告)日：1990-01-30
申请号：US285348
申请日：1988-12-14
申请人： Eldon J. Zorinsky , David B. Spratt , James D. Guillory
发明人： Eldon J. Zorinsky , David B. Spratt , James D. Guillory
IPC分类号： H01L21/285 , H01L21/331 , H01L21/762 , H01L21/84 , H01L29/735
CPC分类号： H01L29/66265 , H01L21/28525 , H01L21/76264 , H01L21/84 , H01L29/735 , H01L21/76281
摘要： A horizontal structure transistor is fabricated in a shallow epitaxial island which is completely surrounded by an insulator, such as oxide. The transistor has base and emitter regions which are diffused into the island from the same mask so that the base width is controllable and remains constant with respect to the emitter. A polysilicon base contact rests on top of the island and is isolated from the emitter and collector regions by an oxide layer. The horizontal structure transistor can easily be fabricated to include complementary bipolar transistors and complementary IGFET devices on the same substrate.
摘要翻译：一个水平结构晶体管制造在一个完全被诸如氧化物之类的绝缘体包围的浅外延岛中。晶体管具有从相同掩模扩散到岛中的基极和发射极区域，使得基极宽度是可控的并且相对于发射极保持恒定。多晶硅基极接触放置在岛的顶部，并通过氧化物层与发射极和集电极区隔离。水平结构晶体管可以容易地制造成在相同的衬底上包括互补双极晶体管和互补的IGFET器件。

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