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    • 1. 发明授权
    • Driver circuit for driving an analog device
    • 用于驱动模拟设备的驱动电路
    • US5121011A
    • 1992-06-09
    • US708879
    • 1991-05-31
    • Eiji OhyaSachito HoriuchiToshio Hanazawa
    • Eiji OhyaSachito HoriuchiToshio Hanazawa
    • H03F3/30
    • H03F3/3008
    • An output circuit comprises first and second transistors connected in series between a first voltage source and an second voltage source such that the first and second transistors are turned on and turned off respectively in response to an input logic signal and a logic inversion thereof, third and fourth transistors connected in series between a third voltage source and fourth voltage source such that the third and fourth transistors are turned on and turned off respectively in response to the logic inversion of the input logic signal and the input logic signal, first and second power transistors connected in series between a fifth voltage source and a sixth voltage source such that the first power transistor is turned on in response to the turning-on of the first transistor and turned off in response to the turning-on of the second transistor, the second power transistor is turned on in response to the turning-on of the third transistor and turned off in response to the turning-on of the fourth transistor, wherein there are provided a first drive control circuit for detecting the turning-on of the second power transistor and disabling the turning-on of the first transistor with a delay such that the turning-on of the first transistor is prohibited for a predetermined interval even after the second power transistor is turned on following a turned off state and a second drive control circuit for detecting the turning-on of the first power transistor and disabling the turning-on of the third transistor with a delay such that the turning-on of the third transistor is prohibited for a predetermined time interval even after the first power transistor is turned on following a turned off state.
    • 输出电路包括串联连接在第一电压源和第二电压源之间的第一和第二晶体管,使得第一和第二晶体管响应于输入逻辑信号及其逻辑反相分别导通和截止,第三和第二晶体管 第四晶体管串联连接在第三电压源和第四电压源之间,使得第三和第四晶体管分别响应于输入逻辑信号和输入逻辑信号的逻辑反相导通和截止,第一和第二功率晶体管 串联连接在第五电压源和第六电压源之间,使得第一功率晶体管响应于第一晶体管的导通而导通,并且响应于第二晶体管的导通而截止,第二 功率晶体管响应于第三晶体管的导通而导通,并且响应于导通而截止 第四晶体管,其中提供有第一驱动控制电路,用于检测第二功率晶体管的导通并且以延迟来禁止第一晶体管的导通,使得第一晶体管的导通被禁止 即使在断开状态之后第二功率晶体管导通之后,也具有预定间隔,以及第二驱动控制电路,用于检测第一功率晶体管的导通,并且使得第三晶体管的导通以延迟为止, 即使在关闭状态之后第一功率晶体管接通之后,也禁止第三晶体管的接通预定时间间隔。