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1. 发明授权

US06311281B1 Apparatus and method for changing processor clock ratio settings 有权
标题翻译：改变处理器时钟比设置的装置和方法
公开(公告)号：US06311281B1
公开(公告)日：2001-10-30
申请号：US09261058
申请日：1999-03-02
申请人： Edwin J. Pole, II , John T. Orton , Cau L. Nguyen , Gurbir Singh , Xia Dai , Ravi Nagaraj
发明人： Edwin J. Pole, II , John T. Orton , Cau L. Nguyen , Gurbir Singh , Xia Dai , Ravi Nagaraj
IPC分类号： G06F104
CPC分类号： G06F1/08 , H03L7/06
摘要： A processor has an external pin that can be asserted to lock in new clock ratio information dynamically. A state machine of the processor defines a stop grant state that is utilized to halt the internal clocking signal of the processor. A storage location, such as a register, is utilized to load new clock frequency information into the clock generator circuit of the processor. De-asserting the external pin of the processor causes the processor to resume normal operations, but at the newly set clock frequency.
摘要翻译：一个处理器有一个外部引脚，可以被断言，以动态锁定新的时钟比率信息。处理器的状态机定义用于停止处理器的内部时钟信号的停止许可状态。诸如寄存器的存储位置被用于将新的时钟频率信息加载到处理器的时钟发生器电路中。取消断言处理器的外部引脚使处理器恢复正常操作，但处于新设定的时钟频率。

2. 发明授权

US6118306A Changing clock frequency 有权
标题翻译：改变时钟频率
公开(公告)号：US6118306A
公开(公告)日：2000-09-12
申请号：US302931
申请日：1999-04-30
申请人： John T. Orton , Cau L. Nguyen , Gurbir Singh , Xia Dai , Raviprakash Nagaraj , Edwin J. Pole, II
发明人： John T. Orton , Cau L. Nguyen , Gurbir Singh , Xia Dai , Raviprakash Nagaraj , Edwin J. Pole, II
IPC分类号： G01R31/30 , G01R23/02
CPC分类号： G06F1/324 , G01R31/3016 , G06F1/3296 , Y02B60/1217 , Y02B60/1285
摘要： A system includes a component (e.g., a processor) that includes a clock generator that generates an internal clock running at a frequency. A controller generates a clock frequency change indication and places the component into a low activity state (e.g., deep sleep, stop grant, or other state). The clock generator is reset by the clock frequency change indication to change the clock's frequency while the component is in the low activity state. Storage elements containing different values are selectable to set the clock frequency. The storage elements include fuse banks and input pins.
摘要翻译：一种系统包括一个组件（例如处理器），该组件包括产生以一个频率运行的内部时钟的时钟发生器。控制器产生时钟频率变化指示并将组件置于低活动状态（例如，深度睡眠，停止授权或其他状态）。时钟发生器由时钟频率变化指示复位，以在组件处于低活动状态时更改时钟频率。可以选择包含不同值的存储元件来设置时钟频率。存储元件包括熔丝组和输入引脚。

3. 发明授权

US06272642B1 Managing a system's performance state 有权
公开(公告)号：US06272642B1
公开(公告)日：2001-08-07
申请号：US09204896
申请日：1998-12-03
申请人： Edwin J. Pole, II , Scott R. Rushford , Eric S. Swartzendruber , Xia Dai
发明人： Edwin J. Pole, II , Scott R. Rushford , Eric S. Swartzendruber , Xia Dai
IPC分类号： G06F126
摘要： A system includes a component, a detector adapted to detect generation of a power management event, and a controller adapted to transition the component from a first performance mode to a lower activity state in response to the power management event. The controller is adapted to change a setting of the component to a second, different performance mode while the component is in the lower activity state. The power management event may be generated in response to a change in the system's power source, an over-temperature condition, or a user command.

4. 发明授权

US06795896B1 Methods and apparatuses for reducing leakage power consumption in a processor 有权
标题翻译：用于减少处理器中的泄漏功率消耗的方法和装置
公开(公告)号：US06795896B1
公开(公告)日：2004-09-21
申请号：US09676149
申请日：2000-09-29
申请人： Frank Hart , Edwin J. Pole, II
发明人： Frank Hart , Edwin J. Pole, II
IPC分类号： G06F1200
CPC分类号： G06F1/3275 , G06F1/3203 , G06F12/0802 , G06F12/0831 , G06F2212/1028 , Y02D10/13 , Y02D10/14
摘要： A method of reducing power leakage consumption in a processor by shutting off power to the cache memory when the processor is idle. The contents of the cache memory are written to a low leakage memory such as SDRAM or main memory. The power to the cache memory is then cut off and remains off until the occurrence of a system event. While power to the cache memory remains off, the cache memory interface is left operational so that the portion of the cache memory image stored in other memory is marked invalid if the corresponding data in main memory has been modified. Upon the occurrence of the system event the cache memory contents are automatically restored to the cache memory within a specified time.
摘要翻译：一种当处理器空闲时通过关闭高速缓冲存储器的电力来减少处理器中的功率泄漏消耗的方法。高速缓冲存储器的内容被写入诸如SDRAM或主存储器的低泄漏存储器。然后，高速缓冲存储器的电源被切断并保持关闭直到发生系统事件。当高速缓冲存储器的电源保持关闭时，高速缓存存储器接口保持运行，使得存储在其他存储器中的高速缓存存储器映像的部分如果主存储器中的对应数据被修改则被标记为无效。当系统事件发生时高速缓存存储器内容将在指定时间内自动恢复到高速缓冲存储器。

5. 发明授权

US06496888B1 Incorporation of bus ratio strap options in chipset logic 失效
标题翻译：在芯片组逻辑中加入总线比率带选项
公开(公告)号：US06496888B1
公开(公告)日：2002-12-17
申请号：US09397159
申请日：1999-09-15
申请人： Edwin J. Pole, II
发明人： Edwin J. Pole, II
IPC分类号： G06F132
CPC分类号： G06F1/3253 , G06F1/32 , G06F1/3203 , Y02D10/151
摘要： A method for incorporating bus ratio strap options in chipset logic. The method of one embodiment first fabricates a register and multiplexer in chipset logic. The register is programmed with a bus ratio setting. A bus ratio setting is selected to be the output from the multiplexer. The selected bus ratio setting is driven out from the multiplexer to output pins.
摘要翻译：一种在芯片组逻辑中并入总线比率带选项的方法。一个实施例的方法首先在芯片组逻辑中制造寄存器和多路复用器。寄存器用总线比设置编程。总线比设置被选择为多路复用器的输出。所选择的总线比率设置从多路复用器输出到输出引脚。

6. 发明授权

US07069456B2 Method and apparatus facilitating direct access to a serial ATA device by an autonomous subsystem 失效
公开(公告)号：US07069456B2
公开(公告)日：2006-06-27
申请号：US09752263
申请日：2000-12-28
申请人： David S. Bormann , Chao-Hsin Chi , Frank P. Hart , Edwin J. Pole, II , Dong Tieu
发明人： David S. Bormann , Chao-Hsin Chi , Frank P. Hart , Edwin J. Pole, II , Dong Tieu
IPC分类号： G06F1/28
CPC分类号： G06F1/3293 , G06F1/3203 , G06F3/0601 , G06F2003/0692 , Y02D10/122
摘要： A method and apparatus for facilitating direct access to a serial Advanced Technology Attachment (ATA) device by an autonomous subsystem in the absence of the main operating system (OS).

7. 发明授权

US06675304B1 System for transitioning a processor from a higher to a lower activity state by switching in and out of an impedance on the voltage regulator 有权
标题翻译：通过切换和调出电压调节器的阻抗，将处理器从较高活动状态转换到较低活动状态的系统
公开(公告)号：US06675304B1
公开(公告)日：2004-01-06
申请号：US09450321
申请日：1999-11-29
申请人： Edwin J. Pole, II , Scott R. Rushford
发明人： Edwin J. Pole, II , Scott R. Rushford
IPC分类号： G06F126
CPC分类号： G06F1/3296 , G06F1/3203 , Y02D10/172
摘要： A voltage regulator may switch in an extra load when the voltage regulator changes from a higher to a lower output level in response to a processor change of state in a processor-based system. The additional load at the lower voltage level in the processor-based system may decrease the latency in the voltage level transistor, improving processor performance.
摘要翻译：当电压调节器响应于基于处理器的系统中的处理器状态变化而从更高的输出电平变化到更低的输出电平时，电压调节器可以切换额外的负载。基于处理器的系统中较低电压电平下的额外负载可能会降低电压电平晶体管的延迟，从而提高处理器性能。

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