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1. 发明授权

US09189230B2 Method and system to provide concurrent user-level, non-privileged shared resource thread creation and execution 有权
标题翻译：方法和系统提供并发用户级，非特权共享资源线程的创建和执行
公开(公告)号：US09189230B2
公开(公告)日：2015-11-17
申请号：US10816103
申请日：2004-03-31
申请人： Edward T. Grochowski , Hong Wang , John P. Shen , Perry H. Wang , Jamison D. Collins , James P. Held , Partha Kundu , Raya Leviathan , Tin-Fook Ngai
发明人： Edward T. Grochowski , Hong Wang , John P. Shen , Perry H. Wang , Jamison D. Collins , James P. Held , Partha Kundu , Raya Leviathan , Tin-Fook Ngai
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30003 , G06F9/30087 , G06F9/3009 , G06F9/30101 , G06F9/3013 , G06F9/384 , G06F9/3851
摘要： A method and system to provide user-level multithreading are disclosed. The method according to the present techniques comprises receiving programming instructions to execute one or more shared resource threads (shreds) via an instruction set architecture (ISA). One or more instruction pointers are configured via the ISA; and the one or more shreds are executed simultaneously with a microprocessor, wherein the microprocessor includes multiple instruction sequencers.
摘要翻译：公开了提供用户级多线程的方法和系统。根据本技术的方法包括接收经由指令集架构（ISA）执行一个或多个共享资源线程（碎片）的编程指令。一个或多个指令指针通过ISA配置; 并且一个或多个碎片与微处理器同时执行，其中微处理器包括多个指令定序器。

2. 发明申请

US20180225118A1 METHOD AND SYSTEM TO PROVIDE USER-LEVEL MULTITHREADING 审中-公开
公开(公告)号：US20180225118A1
公开(公告)日：2018-08-09
申请号：US15943614
申请日：2018-04-02
申请人： Ed Grochowski , Hong Wang , John P. Shen , Perry H. Wang , Jamison D. Collins , James Held , Partha Kundu , Raya Leviathan , Tin-Fook Ngai
发明人： Ed Grochowski , Hong Wang , John P. Shen , Perry H. Wang , Jamison D. Collins , James Held , Partha Kundu , Raya Leviathan , Tin-Fook Ngai
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30003 , G06F9/30087 , G06F9/3009 , G06F9/30101 , G06F9/3013 , G06F9/384 , G06F9/3851
摘要： A method and system to provide user-level multithreading are disclosed. The method according to the present techniques comprises receiving programming instructions to execute one or more shared resource threads (shreds) via an instruction set architecture (ISA). One or more instruction pointers are configured via the ISA; and the one or more shreds are executed simultaneously with a microprocessor, wherein the microprocessor includes multiple instruction sequencers.

3. 发明申请

US20180225117A1 METHOD AND SYSTEM TO PROVIDE USER-LEVEL MULTITHREADING 审中-公开
公开(公告)号：US20180225117A1
公开(公告)日：2018-08-09
申请号：US15943611
申请日：2018-04-02
申请人： Ed Grochowski , Hong Wang , John P. Shen , Perry H. Wang , Jamison D. Collins , James Held , Partha Kundu , Raya Leviathan , Tin-Fook Ngai
发明人： Ed Grochowski , Hong Wang , John P. Shen , Perry H. Wang , Jamison D. Collins , James Held , Partha Kundu , Raya Leviathan , Tin-Fook Ngai
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30003 , G06F9/30087 , G06F9/3009 , G06F9/30101 , G06F9/3013 , G06F9/384 , G06F9/3851
摘要： A method and system to provide user-level multithreading are disclosed. The method according to the present techniques comprises receiving programming instructions to execute one or more shared resource threads (shreds) via an instruction set architecture (ISA). One or more instruction pointers are configured via the ISA; and the one or more shreds are executed simultaneously with a microprocessor, wherein the microprocessor includes multiple instruction sequencers.

4. 发明申请

US20110072234A1 Providing Hardware Support For Shared Virtual Memory Between Local And Remote Physical Memory 有权
标题翻译：为本地和远程物理内存之间的共享虚拟内存提供硬件支持
公开(公告)号：US20110072234A1
公开(公告)日：2011-03-24
申请号：US12562477
申请日：2009-09-18
申请人： Gautham N. Chinya , Hong Wang , Deepak A. Mathaikutty , Jamison D. Collins , Ethan Schuchman , James P. Held , Ajay V. Bhatt , Prashant Sethi , Stephen F. Whalley
发明人： Gautham N. Chinya , Hong Wang , Deepak A. Mathaikutty , Jamison D. Collins , Ethan Schuchman , James P. Held , Ajay V. Bhatt , Prashant Sethi , Stephen F. Whalley
IPC分类号： G06F12/10 , G06F12/00
CPC分类号： G06F12/1036 , G06F12/1027 , G06F12/121 , G06F2212/254
摘要： In one embodiment, the present invention includes a memory management unit (MMU) having entries to store virtual address to physical address translations, where each entry includes a location indicator to indicate whether a memory location for the corresponding entry is present in a local or remote memory. In this way, a common virtual memory space can be shared between the two memories, which may be separated by one or more non-coherent links. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括具有存储虚拟地址到物理地址转换的条目的存储器管理单元（MMU），其中每个条目包括位置指示符，以指示相应条目的存储器位置是否存在于本地或远程记忆。以这种方式，可以在两个存储器之间共享公共虚拟存储器空间，这两个存储器可以由一个或多个非相干链路分隔。描述和要求保护其他实施例。

5. 发明授权

US08719547B2 Providing hardware support for shared virtual memory between local and remote physical memory 有权
标题翻译：为本地和远程物理内存之间的共享虚拟内存提供硬件支持
公开(公告)号：US08719547B2
公开(公告)日：2014-05-06
申请号：US12562477
申请日：2009-09-18
申请人： Gautham N. Chinya , Hong Wang , Deepak A. Mathaikutty , Jamison D. Collins , Ethan Schuchman , James P. Held , Ajay V. Bhatt , Prashant Sethi , Stephen F. Whalley
发明人： Gautham N. Chinya , Hong Wang , Deepak A. Mathaikutty , Jamison D. Collins , Ethan Schuchman , James P. Held , Ajay V. Bhatt , Prashant Sethi , Stephen F. Whalley
IPC分类号： G06F12/10
CPC分类号： G06F12/1036 , G06F12/1027 , G06F12/121 , G06F2212/254
摘要： In one embodiment, the present invention includes a memory management unit (MMU) having entries to store virtual address to physical address translations, where each entry includes a location indicator to indicate whether a memory location for the corresponding entry is present in a local or remote memory. In this way, a common virtual memory space can be shared between the two memories, which may be separated by one or more non-coherent links. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括具有存储虚拟地址到物理地址转换的条目的存储器管理单元（MMU），其中每个条目包括位置指示符，以指示相应条目的存储器位置是否存在于本地或远程记忆。以这种方式，可以在两个存储器之间共享公共虚拟存储器空间，这两个存储器可以由一个或多个非相干链路分隔。描述和要求保护其他实施例。

6. 发明申请

US20140208042A1 PROVIDING HARDWARE SUPPORT FOR SHARED VIRTUAL MEMORY BETWEEN LOCAL AND REMOTE PHYSICAL MEMORY 审中-公开
标题翻译：为当地和远程物理内存之间的共享虚拟内存提供硬件支持
公开(公告)号：US20140208042A1
公开(公告)日：2014-07-24
申请号：US14221741
申请日：2014-03-21
申请人： Gautham N. Chinya , Hong Wang , Deepak A. Mathaikutty , Jamison D. Collins , Ethan Schuchman , James P. Held , Ajay V. Bhatt , Prashant Sethi , Stephen F. Whalley
发明人： Gautham N. Chinya , Hong Wang , Deepak A. Mathaikutty , Jamison D. Collins , Ethan Schuchman , James P. Held , Ajay V. Bhatt , Prashant Sethi , Stephen F. Whalley
IPC分类号： G06F12/10 , G06F12/12
CPC分类号： G06F12/1036 , G06F12/1027 , G06F12/121 , G06F2212/254
摘要： In one embodiment, the present invention includes a memory management unit (MMU) having entries to store virtual address to physical address translations, where each entry includes a location indicator to indicate whether a memory location for the corresponding entry is present in a local or remote memory. In this way, a common virtual memory space can be shared between the two memories, which may be separated by one or more non-coherent links. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括具有存储虚拟地址到物理地址转换的条目的存储器管理单元（MMU），其中每个条目包括位置指示符，以指示相应条目的存储器位置是否存在于本地或远程记忆。以这种方式，可以在两个存储器之间共享公共虚拟存储器空间，这两个存储器可以由一个或多个非相干链路分隔。描述和要求保护其他实施例。

7. 发明授权

US07587584B2 Mechanism to exploit synchronization overhead to improve multithreaded performance 有权
标题翻译：利用同步开销来提高多线程性能的机制
公开(公告)号：US07587584B2
公开(公告)日：2009-09-08
申请号：US11070991
申请日：2005-03-02
申请人： Natalie D. Enright , Jamison D. Collins , Perry Wang , Hong Wang , Xinmin Tran , John Shen , Gad Sheaffer , Per Hammarlund
发明人： Natalie D. Enright , Jamison D. Collins , Perry Wang , Hong Wang , Xinmin Tran , John Shen , Gad Sheaffer , Per Hammarlund
IPC分类号： G06F9/00
CPC分类号： G06F9/3851 , G06F9/3009 , G06F9/4843 , G06F11/3419 , G06F11/348 , G06F2201/86 , G06F2201/88 , G06F2201/885
摘要： Method, apparatus, and program means for a programmable event driven yield mechanism that may activate other threads. In one embodiment, an apparatus includes execution resources to execute a plurality of instructions and an event detector to detect a long latency event associated with a synchronization object. The event detector can cause a first thread switch in response to the long latency event associated with the synchronization object. The apparatus may also include a spin detector to detect that the synchronization object is a contended synchronization object. The spin detector can cause a second thread switch in response to the detection of the contended synchronization object to enable a spin detect response.
摘要翻译：用于可激活其他线程的可编程事件驱动产量机制的方法，装置和程序装置。在一个实施例中，装置包括执行多个指令的执行资源和用于检测与同步对象相关联的长延迟事件的事件检测器。事件检测器可以响应于与同步对象相关联的长等待时间事件而导致第一线程切换。该装置还可以包括检测同步对象是竞争同步对象的自旋检测器。响应于竞争的同步对象的检测，自旋检测器可以引起第二线程切换以启用自旋检测响应。

8. 发明申请

US20090158248A1 Compiler and Runtime for Heterogeneous Multiprocessor Systems 有权
标题翻译：用于异构多处理器系统的编译器和运行时
公开(公告)号：US20090158248A1
公开(公告)日：2009-06-18
申请号：US11958307
申请日：2007-12-17
申请人： Michael D. Linderman , Jamison D. Collins , Perry Wang , Hong Wang
发明人： Michael D. Linderman , Jamison D. Collins , Perry Wang , Hong Wang
IPC分类号： G06F9/44
CPC分类号： G06F9/505 , G06F2209/5017
摘要： Presented are embodiments of methods and systems for library-based compilation and dispatch to automatically spread computations of a program across heterogeneous cores in a processing system. The source program contains a parallel-programming keyword, such as mapreduce, from a high-level, library-oriented parallel programming language. The compiler inserts one or more calls for a generic function, associated with the parallel-programming keyword, into the compiled code. A runtime library provides a predicate-based library system that includes multiple hardware specific implementations (“variants”) of the generic function. A runtime dispatch engine dynamically selects the best-available (e.g., most specific) variant, from a bundle of hardware-specific variants, for a given input and machine configuration. That is, the dispatch engine may take into account run-time availability of processing elements, choose one of them, and then select for dispatch an appropriate variant to be executed on the selected processing element. Other embodiments are also described and claimed.
摘要翻译：提出了用于基于库的编译和调度的方法和系统的实施例，以便在处理系统中跨异构核心自动扩展程序的计算。源程序包含一个并行编程关键字，如mapreduce，来自高级的面向库的并行编程语言。编译器将一个或多个与并行编程关键字关联的通用函数的调用插入到编译代码中。运行时库提供了一个基于谓词的库系统，它包含通用函数的多个硬件特定实现（“变体”）。对于给定的输入和机器配置，运行时调度引擎从一组特定于硬件的变体动态地选择最佳可用（例如，最具体的）变体。也就是说，调度引擎可以考虑处理元件的运行时间可用性，选择其中之一，然后选择在所选择的处理元件上调度要执行的适当变体。还描述和要求保护其他实施例。

9. 发明授权

US08296743B2 Compiler and runtime for heterogeneous multiprocessor systems 有权
标题翻译：异构多处理器系统的编译器和运行时
公开(公告)号：US08296743B2
公开(公告)日：2012-10-23
申请号：US11958307
申请日：2007-12-17
申请人： Michael D. Linderman , Jamison D. Collins , Perry Wang , Hong Wang
发明人： Michael D. Linderman , Jamison D. Collins , Perry Wang , Hong Wang
IPC分类号： G06F9/45
CPC分类号： G06F9/505 , G06F2209/5017
摘要： Presented are embodiments of methods and systems for library-based compilation and dispatch to automatically spread computations of a program across heterogeneous cores in a processing system. The source program contains a parallel-programming keyword, such as mapreduce, from a high-level, library-oriented parallel programming language. The compiler inserts one or more calls for a generic function, associated with the parallel-programming keyword, into the compiled code. A runtime library provides a predicate-based library system that includes multiple hardware specific implementations (“variants”) of the generic function. A runtime dispatch engine dynamically selects the best-available (e.g., most specific) variant, from a bundle of hardware-specific variants, for a given input and machine configuration. That is, the dispatch engine may take into account run-time availability of processing elements, choose one of them, and then select for dispatch an appropriate variant to be executed on the selected processing element. Other embodiments are also described and claimed.
摘要翻译：提出了用于基于库的编译和调度的方法和系统的实施例，以便在处理系统中跨异构核心自动扩展程序的计算。源程序包含一个并行编程关键字，如mapreduce，来自高级的面向库的并行编程语言。编译器将一个或多个与并行编程关键字关联的通用函数的调用插入到编译代码中。运行时库提供了一个基于谓词的库系统，其中包含通用功能的多个硬件特定实现（变体）。对于给定的输入和机器配置，运行时调度引擎从一组特定于硬件的变体动态地选择最佳可用（例如，最具体的）变体。也就是说，调度引擎可以考虑处理元件的运行时间可用性，选择其中之一，然后选择在所选择的处理元件上调度要执行的适当变体。还描述和要求保护其他实施例。

10. 发明授权

US08621153B2 Microcode refactoring and caching 有权
标题翻译：微码重构和缓存
公开(公告)号：US08621153B2
公开(公告)日：2013-12-31
申请号：US12978583
申请日：2010-12-26
申请人： Jamison D. Collins
发明人： Jamison D. Collins
IPC分类号： G06F12/00
CPC分类号： G06F12/0875 , G06F9/24 , G06F9/3017 , G06F9/30178 , G06F9/3802
摘要： Methods and apparatus relating to microcode refactoring and/or caching are described. In some embodiments, an off-chip structure that stores microcode is shared by multiple processor cores. Other embodiments are also described and claimed.
摘要翻译：描述与微代码重构和/或高速缓存相关的方法和装置。在一些实施例中，存储微码的片外结构由多个处理器核共享。还描述和要求保护其他实施例。

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