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1. 发明授权

US5517515A Multichip module with integrated test circuitry disposed within interposer substrate 失效
标题翻译：集成测试电路的多芯片模块设置在内插器基板内
公开(公告)号：US5517515A
公开(公告)日：1996-05-14
申请号：US292120
申请日：1994-08-17
申请人： Edward J. Spall , Thomas M. Storey
发明人： Edward J. Spall , Thomas M. Storey
IPC分类号： G01R31/28 , G01R31/3185 , H01L21/66 , H03K19/00 , G06F11/00
CPC分类号： G01R31/318536 , G01R31/318505
摘要： A multichip module (MCM) and associated fabrication technique are presented wherein a test circuit is disposed within the interposer substrate of the MCM to facilitate testing of the module's integrated circuit chips and testing of the interconnect wiring between integrated circuit chips. The test circuitry, disposed within the interposer substrate comprises semiconductor logic circuitry that electrically connects to the integrated circuit chips of the module. In the various multiplexer latch and shift register latch embodiments disclosed, active test circuitry within the interposer substrate is minimized and is essentially transparent to the integrated circuit chip designs incorporated in the MCM.
摘要翻译：提出了一种多芯片模块（MCM）和相关的制造技术，其中测试电路设置在MCM的插入器基板内，以便于模块的集成电路芯片的测试和集成电路芯片之间的互连布线的测试。设置在插入器衬底内的测试电路包括电连接到模块的集成电路芯片的半导体逻辑电路。在公开的各种复用器锁存器和移位寄存器锁存器实施例中，内插器衬底内的有源测试电路被最小化，并且对于并入MCM中的集成电路芯片设计基本上是透明的。

2. 发明授权

US06883113B2 System and method for temporally isolating environmentally sensitive integrated circuit faults 失效
标题翻译：对环境敏感的集成电路故障进行暂时隔离的系统和方法
公开(公告)号：US06883113B2
公开(公告)日：2005-04-19
申请号：US10125900
申请日：2002-04-18
申请人： Bruce McWilliam , Ronald Todd , Thomas M. Storey
发明人： Bruce McWilliam , Ronald Todd , Thomas M. Storey
IPC分类号： G01R31/317 , G01R31/3185 , G06F11/00
CPC分类号： G01R31/318552 , G01R31/31725
摘要： A procedure for temporally isolating an environmentally dependent integrated circuit fault includes the steps of determining a marginally failing and a minimally passing environmental condition corresponding to the fault; identifying a clock cycle Tmax at which the fault was first detected; determining a candidate clock cycle at which the fault may have occurred; and iteratively a) applying test pattern subsets from an initial clock cycle through the candidate clock cycle under the marginally failing environmental condition; b) applying remaining test patterns under the minimally passing environmental condition; and c) adjusting the candidate clock cycle based upon whether the fault occurred during test pattern subset application up through the candidate clock cycle under the marginally failing environmental condition. Candidate clock cycle adjustment in accordance with a binary search technique enables determination of an exact clock cycle at which the fault occurred in a maximum of Log2 (Tmax+1) iterations.
摘要翻译：用于时间上隔离环境依赖的集成电路故障的过程包括确定与故障相对应的边缘故障和最小通过的环境条件的步骤; 识别故障首先被检测到的时钟周期T最大值; 确定可能发生故障的候选时钟周期; 并迭代地a）在初始时钟周期内将测试模式子集应用于边缘化环境条件下的候选时钟周期; b）在最小通过的环境条件下应用剩余的测试图案; 以及c）基于在所述稍微失败的环境条件下通过候选时钟周期在测试模式子集应用期间是否发生故障来调整候选时钟周期。根据二进制搜索技术的候选时钟周期调整使得能够以最大的Log 2（T max）+1迭代确定故障发生的精确时钟周期。

3. 发明授权

US06697978B1 Method for testing of known good die 失效
标题翻译：测试已知好模具的方法
公开(公告)号：US06697978B1
公开(公告)日：2004-02-24
申请号：US09624247
申请日：2000-07-24
申请人： Michael J. Bear , Thomas M. Storey
发明人： Michael J. Bear , Thomas M. Storey
IPC分类号： G11C2900
CPC分类号： G11C29/50012 , G11C29/08 , G11C29/50016 , G11C2029/5006
摘要： Multi-pattern data retention testing and iterative change of measurement testing are used for the production of Known Good Dies. Multi-pattern data testing of a memory such as an SRAM comprises writing at Vdd, reduction of Vdd, restoration of Vdd, reading of the memory, and comparison of write patterns to read patterns to determine accuracy of data retention. Iterative or change of measurement testing involves repeated testing of a die to determine changes in Iddq, changes in multi-pattern data retention, or other changes in chip operating parameters. Defect activating test may be used in combination with change of measurement testing or with multi-pattern data retention testing.
摘要翻译：多模式数据保留测试和测量测试的迭代更改用于生产已知好的模型。诸如SRAM的存储器的多模式数据测试包括以Vdd写入，减少Vdd，恢复Vdd，读取存储器，以及将写入模式与读取模式的比较，以确定数据保留的准确性。测量测试的迭代或更改涉及对芯片的重复测试，以确定Iddq的变化，多模式数据保留的变化或芯片操作参数的其他变化。缺陷激活测试可与测量测试的更改或多模式数据保留测试结合使用。

4. 发明授权

US4852061A High density, high performance register file having improved clocking means 失效
标题翻译：高密度，高性能的寄存器文件具有改进的时钟装置
公开(公告)号：US4852061A
公开(公告)日：1989-07-25
申请号：US313300
申请日：1989-02-21
申请人： Henry C. Baron , Johnny J. LeBlanc , Thomas M. Storey , Joseph W. Yoder
发明人： Henry C. Baron , Johnny J. LeBlanc , Thomas M. Storey , Joseph W. Yoder
IPC分类号： G11C7/10
CPC分类号： G11C7/106 , G11C7/1051 , G11C2207/108
摘要： The improved register file includes an array of storage cells arranged in columns and rows, each column having a pair of bit lines for writing into the cell. Each storage cell includes a flip-flop cell having a first storage node connected to a respective read line which is unique for that cell. A read address latch has an enabling input connected to the master clock signal which is the same master clock signal for the LSSD logic on the integrated circuit chip. The read address latch applies its decoded output to a multiplexer which selects those read lines coming from one of the rows of storage cells in the array, and applies those selected read lines to an output storage cell array. The output storage cell array is enabled by a slave clock signal which is the same slave clock signal employed in the LSSD logic on the same integrated circuit chip. The output storage cell array stores the data from the selected read lines out of the multiplexer. The multiplexer propagates the data signals output from the read lines and performs the selection during the delay period between the master clock signal and the slave clock signal. Thus, the circuit makes use of the dead time between the master clock signal and the slave clock signal which was heretofore wasted, in performing the selection of the read lines for latching in the output storage cell array. The feature of connecting separate read lines to each respective storage cell in the array allows the independent accessing of different register rows in the register file for reading and writing, during the same logic cycle defined by the interval for the occurrence of both the master and the slave clock pulses.
摘要翻译：改进的寄存器文件包括以列和行排列的存储单元的阵列，每列具有用于写入单元的一对位线。每个存储单元包括触发器单元，其具有连接到该单元的唯一的相应读取线的第一存储节点。读地址锁存器具有连接到主时钟信号的使能输入，该主时钟信号与集成电路芯片上的LSSD逻辑相同的主时钟信号。读地址锁存器将其解码的输出应用于多路复用器，该多路复用器选择来自阵列中的一行存储单元的读取线，并将这些所选择的读取行应用于输出存储单元阵列。输出存储单元阵列由在同一集成电路芯片上的LSSD逻辑中使用的从时钟信号相同的从时钟信号使能。输出存储单元阵列将来自所选读取线的数据存储在多路复用器中。多路复用器传播从读线输出的数据信号，并在主时钟信号和从时钟信号之间的延迟周期内进行选择。因此，在执行选择用于锁定在输出存储单元阵列中的读取线的情况下，电路利用原始时钟信号和从时钟信号之间的死区时间。将单独的读取线连接到阵列中的每个相应的存储单元的特征允许在寄存器文件中的不同寄存器行的独立访问以在由主器件和发生器的发生的间隔定义的相同逻辑周期期间进行读取和写入从时钟脉冲。

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