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1. 发明申请

US20070014229A1 Protocol engine for processing data in a wireless transmit/receive unit 有权
标题翻译：用于在无线发射/接收单元中处理数据的协议引擎
公开(公告)号：US20070014229A1
公开(公告)日：2007-01-18
申请号：US11474718
申请日：2006-06-26
申请人： Edward Hepler , Robert Gazda , Alexander Reznik
发明人： Edward Hepler , Robert Gazda , Alexander Reznik
IPC分类号： H04J11/00
CPC分类号： G06F13/1663 , H04L49/90 , H04L49/901 , H04L49/9057 , H04L49/9094 , H04L67/04 , H04L69/12 , H04L69/22 , H04L69/324 , H04W88/02
摘要： A protocol engine (PE) for processing data within a protocol stack in a wireless transmit/receive unit (WTRU) is disclosed. The protocol stack executes decision and control operations. The data processing and re-formatting which was performed in a conventional protocol stack is removed from the protocol stack and performed by the PE. The protocol stack issues a control word for processing data and the PE processes the data based on the control word. Preferably, the WTRU includes a shared memory and a second memory. The shared memory is used as a data block place holder to transfer the data amongst processing entities. For transmit processing, the PE retrieves source data from the second memory and processes the data while moving the data to the shared memory based on the control word. For receive processing, the PE retrieves received data from the shared memory and processes it while moving the data to the second memory.
摘要翻译：公开了一种用于处理无线发射/接收单元（WTRU）中的协议栈内的数据的协议引擎（PE）。协议栈执行决策和控制操作。在传统协议栈中执行的数据处理和重新格式化从协议栈中删除，并由PE执行。协议栈发出处理数据的控制字，PE根据控制字处理数据。优选地，WTRU包括共享存储器和第二存储器。共享存储器用作数据块占位符以在处理实体之间传送数据。对于发送处理，PE从第二存储器检索源数据，并且在基于控制字将数据移动到共享存储器的同时处理数据。对于接收处理，PE从共享存储器中检索接收到的数据，并在将数据移动到第二个存储器的同时进行处理。

2. 发明申请

US20050262344A1 Data-mover controller with plural registers for supporting ciphering operations 失效
标题翻译：具有多个寄存器的数据移动器控制器，用于支持加密操作
公开(公告)号：US20050262344A1
公开(公告)日：2005-11-24
申请号：US10878729
申请日：2004-06-28
申请人： Edward Hepler , Robert Gazda
发明人： Edward Hepler , Robert Gazda
IPC分类号： G06F21/00 , H04L9/00 , H04L29/06
CPC分类号： H04L63/0428 , G06F21/72 , G06F21/85 , H04W12/02
摘要： A data processing system ciphers and transfers data between a first memory unit and a second memory unit, such as, for example, between a share memory architecture (SMA) static random access memory (SRAM) and a double data rate (DDR) synchronous dynamic random access memory (SDRAM). The system includes a ciphering engine and a data-mover controller. The data-mover controller includes at least one register having a field that specifies whether or not the transferred data should be ciphered. If the field specifies that the transferred data should be ciphered, the field also specifies the type of ciphering that is to be performed, such as a third generation partnership project (3GPP) standardized confidentially cipher algorithm “f8” or integrity cipher algorithm “f9”.
摘要翻译：数据处理系统在第一存储器单元和第二存储器单元之间加密和传输数据，例如在共享存储器架构（SMA）静态随机存取存储器（SRAM）和双倍数据速率（DDR）同步动态随机存取存储器（SDRAM）。该系统包括加密引擎和数据移动器控制器。数据移动器控制器包括至少一个具有指定所传输的数据是否应被加密的字段的寄存器。如果该字段指定传输的数据应该被加密，则该字段还指定要执行的加密类型，例如第三代合作伙伴计划（3GPP）标准化的机密密码算法“f8”或完整性密码算法“f9” 。

3. 发明申请

US20070060142A1 Method and apparatus for efficient operation of an enhanced dedicated channel 失效
标题翻译：增强专用信道有效运行的方法和装置
公开(公告)号：US20070060142A1
公开(公告)日：2007-03-15
申请号：US11471402
申请日：2006-06-19
申请人： Alexander Reznik , Edward Hepler , Guodong Zhang , Harry Smith , Peter Wang , Renuka Racha , Robert Gazda , Stephen Terry
发明人： Alexander Reznik , Edward Hepler , Guodong Zhang , Harry Smith , Peter Wang , Renuka Racha , Robert Gazda , Stephen Terry
IPC分类号： H04Q7/20
CPC分类号： H04W72/0406 , H04L1/1812 , H04L1/1854 , H04L1/1887 , H04L1/1896
摘要： A method and apparatus for efficient operation of an enhanced dedicated channel (E-DCH) are disclosed. A physical layer processing includes computation of various control parameters followed by actual processing of the data to be transmitted. In accordance with the present invention, the computation of the control parameters is performed asynchronously from the associated data operation. A medium access control (MAC) layer provides information needed for computation of the control parameters to the physical layer as early as possible, while the data is being processed in parallel. The provided data includes a hybrid automatic repeat request (H-ARQ) profile, a transport block size, power offset, or the like. By sending this data to the physical layer before MAC-e processing is complete, the latency constraint can be significantly relaxed.
摘要翻译：公开了一种用于增强专用信道（E-DCH）的有效操作的方法和装置。物理层处理包括各种控制参数的计算，随后实际处理要发送的数据。根据本发明，控制参数的计算是从关联的数据操作中异步执行的。介质访问控制（MAC）层在数据被并行处理的同时尽可能早地向物理层提供控制参数的计算所需的信息。提供的数据包括混合自动重传请求（H-ARQ）简档，传输块大小，功率偏移等。通过在MAC-e处理完成之前将该数据发送到物理层，可以显着放宽等待时间约束。

4. 发明申请

US20060039330A1 High speed downlink packet access co-processor for upgrading the capabilities of an existing modem host 审中-公开
标题翻译：用于升级现有调制解调器主机的能力的高速下行链路分组接入协处理器
公开(公告)号：US20060039330A1
公开(公告)日：2006-02-23
申请号：US11184331
申请日：2005-07-19
申请人： William Hackett , Robert DiFazio , Edward Hepler , Alexander Reznik , Douglas Castor , Ariela Zeira , Robert Gazda , John Kaewell
发明人： William Hackett , Robert DiFazio , Edward Hepler , Alexander Reznik , Douglas Castor , Ariela Zeira , Robert Gazda , John Kaewell
IPC分类号： H04B7/216
CPC分类号： H04B1/707 , H04B1/406 , H04B2201/70707 , H04B2201/709727 , H04L2025/03509 , H04W88/02
摘要： A wireless transmit/receive unit (WTRU) for processing code division multiple access (CDMA) signals. The WTRU includes a modem host and a high speed downlink packet access (HSDPA) co-processor, which communicate over a plurality of customizable interfaces. The modem host operates in accordance with third generation partnership project (3GPP) Release 4 (R4) standards, and the HSDPA co-processor enhances the wireless communication capabilities of the WTRU as a whole such that the WTRU operates in accordance with 3GPP Release 5 (R5) standards.
摘要翻译：一种用于处理码分多址（CDMA）信号的无线发射/接收单元（WTRU）。 WTRU包括调制解调器主机和通过多个可定制接口进行通信的高速下行链路分组接入（HSDPA）协处理器。调制解调器主机根据第三代合作伙伴计划（3GPP）版本4（R4）标准进行操作，并且HSDPA协处理器整体上增强了WTRU的无线通信能力，使得WTRU根据3GPP版本5（ R5）标准。

5. 发明申请

US20060005111A1 Pipeline architecture for maximum a posteriori (MAP) decoders 失效
标题翻译：最大后验（MAP）解码器的管道架构
公开(公告)号：US20060005111A1
公开(公告)日：2006-01-05
申请号：US11219986
申请日：2005-09-06
申请人： Edward Hepler , Michael Starsinic
发明人： Edward Hepler , Michael Starsinic
IPC分类号： H03M13/03
CPC分类号： H03M13/3905 , H03M13/3972 , H03M13/6505
摘要： The sliding window approach to pipeline maximum a posteriori (MAP) decoder architecture is modified to decrease processing time. Once the forward metrics have been calculated for he first sliding window of the decoder, the reverse metrics for each window are calculated while the forward metrics for the next window are calculated. As each new forward metric is calculated and stored into memory, the forward metric from the previous window is read from memory for use with reverse metric being calculated in calculating extrinsic value. Each forward metric for use in calculating an extrinsic value is written to the same memory location. The calculations can be reversed, reverse metrics being calculated first, followed by reverse metric calculations. Although this architecture as developed for a turbo decoder, all convolution codes can use the MAP algorithm of the present invention.
摘要翻译：流水线最大后验（MAP）解码器架构的滑动窗口方法被修改以减少处理时间。一旦为其解码器的第一滑动窗口计算了前向度量，则在计算下一个窗口的前向量度时，计算每个窗口的反向度量。当每个新的前向度量被计算并存储到存储器中时，从存储器中读取来自前一窗口的前向度量用于在计算外在值时计算的反向度量。用于计算外在值的每个前向量度被写入同一个存储单元。计算可以反转，首先计算反向度量，然后是反向度量计算。虽然为turbo解码器开发的这种架构，但是所有的卷积码都可以使用本发明的MAP算法。

6. 发明授权

US07092432B2 Node-B/base station rake finger pooling 有权
标题翻译：节点B /基站耙指池
公开(公告)号：US07092432B2
公开(公告)日：2006-08-15
申请号：US10838634
申请日：2004-05-04
申请人： John David Kaewell, Jr. , Timothy Berghius , Jan Meyer , Peter Bohnhoff , Alexander Reznik , Edward Hepler , Michael Koch , William C. Hackett , David S. Bass , Clyde N. Robbins
发明人： John David Kaewell, Jr. , Timothy Berghius , Jan Meyer , Peter Bohnhoff , Alexander Reznik , Edward Hepler , Michael Koch , William C. Hackett , David S. Bass , Clyde N. Robbins
IPC分类号： H04B1/707
CPC分类号： H04B1/712 , H04B1/7117 , H04B7/0491 , H04B2201/7071 , H04B2201/70711
摘要： A Node-B/base station receiver comprises at least one antenna for receiving signals. Each finger of a pool of reconfigurable Rake fingers recovers a multipath component of a user and is assigned a code of the user, a code phase of the multipath component and an antenna of the at least one antenna. An antenna/Rake finger pool interface provides each finger of the Rake pool an output of the antenna assigned to that Rake finger. A combiner combines the recovered multipath components for a user to produce data of the user.
摘要翻译：节点B /基站接收机包括用于接收信号的至少一个天线。可重构Rake指针池的每个手指恢复用户的多径分量，并且被分配用户的代码，多径分量的码相位和至少一个天线的天线。天线/耙指池接口为耙池的每个手指提供分配给该耙指的天线的输出。组合器将用于用户的恢复的多路径组件组合以产生用户的数据。

7. 发明申请

US20070258593A1 System for generating pseudorandom sequences 失效
标题翻译：用于生成伪随机序列的系统
公开(公告)号：US20070258593A1
公开(公告)日：2007-11-08
申请号：US11827895
申请日：2007-07-12
申请人： Edward Hepler
发明人： Edward Hepler
IPC分类号： H04L9/00
CPC分类号： G06F1/0255 , H04J13/0044 , H04J13/12
摘要： A system for generating pseudorandom codes using a register which contains an identification of the code tree leg of the desired code and a counter which outputs a successive binary sequence. The output from the counter is bit-by-bit ANDed with the output of the register, and those outputs are XORed together to output a single bit. As the counter is sequenced, each count results in a different bit that is output from the XOR gate, resulting in the desired code.
摘要翻译：一种使用包含所需代码的代码树段的标识的寄存器生成伪随机代码的系统和输出连续的二进制序列的计数器。计数器的输出与寄存器的输出逐位AND，并将这些输出异或并输出一位。当计数器被排序时，每个计数导致从XOR门输出的不同位，产生所需的代码。

8. 发明授权

US5432801A Method and apparatus for performing multiple simultaneous error detection on data having unknown format 失效
标题翻译：用于对具有未知格式的数据执行多个同时错误检测的方法和装置
公开(公告)号：US5432801A
公开(公告)日：1995-07-11
申请号：US96322
申请日：1993-07-23
申请人： Edward Hepler
发明人： Edward Hepler
IPC分类号： G11B20/18 , H03M13/00
CPC分类号： G11B20/1833 , H03M13/00
摘要： An error may be detected and corrected from among a plurality of data values retrieved from a compact disk-read only memory (CD-ROM). As a stream of data values which have been retrieved from the CD-ROM are retransmitted by an appropriate DMA device, two different error detection schemes are simultaneously applied to identical copies of the retrieved data. The retrieved data is then evaluated to determine in which format data has been stored on the CD-ROM. A condition value which has been generated by the algorithm corresponding to the determined format of data on the CD-ROM is then evaluated to determine the probability of an error condition in the retrieved data. The two error detection schemes may differ solely in the location of the data values which are evaluated for errors.
摘要翻译：可以从从光盘只读存储器（CD-ROM）检索的多个数据值中检测和校正错误。由于从CD-ROM检索的数据流流被适当的DMA设备重传，所以将两个不同的错误检测方案同时应用于所检索数据的相同副本。然后对所检索的数据进行评估，以确定数据已被存储在CD-ROM上的格式。然后评估由对应于所确定的CD-ROM上的数据格式的算法产生的条件值，以确定检索数据中的错误状况的概率。两个错误检测方案可能仅在为错误评估的数据值的位置上不同。

9. 发明申请

US20070118791A1 Pipeline architecture for maximum a posteriori (MAP) decoders 失效
标题翻译：最大后验（MAP）解码器的管道架构
公开(公告)号：US20070118791A1
公开(公告)日：2007-05-24
申请号：US11653014
申请日：2007-01-12
申请人： Edward Hepler , Michael Starsinic
发明人： Edward Hepler , Michael Starsinic
IPC分类号： H03M13/03
CPC分类号： H03M13/3905 , H03M13/3972 , H03M13/6505
摘要： The sliding window approach to pipeline maximum a posteriori (MAP) decoder architecture is modified to decrease processing time. Once the forward metrics have been calculated for he first sliding window of the decoder, the reverse metrics for each window are calculated while the forward metrics for the next window are calculated. As each new forward metric is calculated and stored into memory, the forward metric from the previous window is read from memory for use with reverse metric being calculated in calculating extrinsic value. Each forward metric for use in calculating an extrinsic value is written to the same memory location. The calculations can be reversed, reverse metrics being calculated first, followed by reverse metric calculations. Although this architecture as developed for a turbo decoder, all convolution codes can use the MAP algorithm of the present invention.
摘要翻译：流水线最大后验（MAP）解码器架构的滑动窗口方法被修改以减少处理时间。一旦为其解码器的第一滑动窗口计算了前向度量，则在计算下一个窗口的前向量度时，计算每个窗口的反向度量。当每个新的前向度量被计算并存储到存储器中时，从存储器中读取来自前一窗口的前向度量用于在计算外在值时计算的反向度量。用于计算外在值的每个前向量度被写入同一个存储单元。计算可以反转，首先计算反向度量，然后是反向度量计算。虽然为turbo解码器开发的这种架构，但是所有的卷积码都可以使用本发明的MAP算法。

10. 发明申请

US20060203893A1 Components and methods for processing in wireless communication data in presence of format uncertainty 失效
标题翻译：在存在格式不确定性的情况下在无线通信数据中处理的组件和方法
公开(公告)号：US20060203893A1
公开(公告)日：2006-09-14
申请号：US11418861
申请日：2006-05-05
申请人： Alexander Reznik , Edward Hepler
发明人： Alexander Reznik , Edward Hepler
IPC分类号： H04B1/707
CPC分类号： H04L1/1829 , H04B1/707 , H04L1/0006 , H04L1/0025 , H04L1/0032 , H04L1/0071
摘要： Components and method are provided to efficiently process wireless communications data where prior knowledge of a specific format of the communication data is not available. A wireless transmit receive unit (WTRU) is configured for use in a wireless communication system where communication data for selected channels is transmitted in system time frames in formats selected from among a set of predefined formats. The WTRU has a receiver, a memory, a received chip rate processor (RCRP) and a format detector. The RCRP is preferably configured to despread each wireless signal of spread data received in each time frame using a minimum spreading code or other appropriate key sequence and to store resultant despread data for each respective time frame in the memory. The format detector is preferably configured to determine the number of physical channels and the respective spreading factor for each physical channel for the wireless signal of spread data.
摘要翻译：提供组件和方法以有效地处理无线通信数据，其中通信数据的特定格式的先前知识不可用。无线发射接收单元（WTRU）被配置为在无线通信系统中使用，其中所选信道的通信数据以系统时间帧的形式从一组预定格式中选出。 WTRU具有接收机，存储器，接收的码片速率处理器（RCRP）和格式检测器。优选地，RCRP被配置为使用最小扩展码或其他适当的密钥序列来解扩每个时间帧中接收的扩展数据的每个无线信号，并且将每个相应时间帧的合成解扩数据存储在存储器中。格式检测器优选地被配置为确定用于扩展数据的无线信号的每个物理信道的物理信道的数量和相应的扩展因子。

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