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1. 发明申请

US20100265772A1 NAND MEMORY DEVICE AND PROGRAMMING METHODS 有权
标题翻译： NAND存储器件和编程方法
公开(公告)号：US20100265772A1
公开(公告)日：2010-10-21
申请号：US12827892
申请日：2010-06-30
申请人： Frankie F. Roohparvar , Ebrahim Abedifard
发明人： Frankie F. Roohparvar , Ebrahim Abedifard
IPC分类号： G11C16/06
CPC分类号： G11C16/0483 , G11C16/12 , G11C16/3459 , G11C2216/14
摘要： A NAND Flash memory device is described that can reduce bit line coupling and floating gate coupling during program and verify operations. Consecutive bit lines of an array row are concurrently programmed as a common page. Floating gate coupling during programming can therefore be reduced. Multiple verify operations are performed on separate bit lines of the page. Bit line coupling can therefore be reduced.
摘要翻译：描述了一种NAND闪存器件，其可以在编程和验证操作期间减少位线耦合和浮动栅极耦合。阵列行的连续位线被同时编程为公共页面。因此可以减少编程期间的浮动栅极耦合。在页面的单独位线上执行多个验证操作。因此可以减少位线耦合。

2. 发明授权

US07751242B2 NAND memory device and programming methods 有权
标题翻译： NAND存储器件和编程方法
公开(公告)号：US07751242B2
公开(公告)日：2010-07-06
申请号：US11215990
申请日：2005-08-30
申请人： Frankie F. Roohparvar , Ebrahim Abedifard
发明人： Frankie F. Roohparvar , Ebrahim Abedifard
IPC分类号： G11C11/34
CPC分类号： G11C16/0483 , G11C16/12 , G11C16/3459 , G11C2216/14
摘要： A NAND Flash memory device is described that can reduce bit line coupling and floating gate coupling during program and verify operations. Consecutive bit lines of an array row are concurrently programmed as a common page. Floating gate coupling during programming can therefore be reduced. Multiple verify operations are performed on separate bit lines of the page. Bit line coupling can therefore be reduced.
摘要翻译：描述了一种NAND闪存器件，其可以在编程和验证操作期间减少位线耦合和浮动栅极耦合。阵列行的连续位线被同时编程为公共页面。因此可以减少编程期间的浮动栅极耦合。在页面的单独位线上执行多个验证操作。因此可以减少位线耦合。

3. 发明授权

US06496425B1 Multiple bit line column redundancy 有权
标题翻译：多位线列冗余
公开(公告)号：US06496425B1
公开(公告)日：2002-12-17
申请号：US09642341
申请日：2000-08-21
申请人： Ebrahim Abedifard , Frankie F. Roohparvar
发明人： Ebrahim Abedifard , Frankie F. Roohparvar
IPC分类号： G11C700
CPC分类号： G11C29/82
摘要： Memory devices having multiple bit line column redundancy are suited for high-performance memory devices, with particular reference synchronous non-volatile memory devices. Such memory devices include bloc of memory cells arranged in columns with each column of memory cells coupled to a local line. Such memory devices further include global bit lines having multiple local bit lines selectively coupled to each global bit line, with each global bit line extending to local bit lines in each memory block of a memory sector. Global bit lines are coupled to sensing devices generally in pairs. Repair of one or more defective columns of memory cells within a sector is effected by providing a redundant grouping of memory cells having a redundant sense amplifier, global bit lines and local bit lines. Each grouping of memory cells contains four or more columns of memory cells. Access requests directed to memory cells within a grouping of memory cells containing a defective column are redirected to a redundant grouping of memory cells. Thus, a defect in one column of memory cells results in replacement of four or more columns of memory cells.
摘要翻译：具有多个位线列冗余的存储器件适用于具有特定参考同步非易失性存储器件的高性能存储器件。这样的存储器件包括以每列存储器单元耦合到本地线的列排列的存储器单元的集合。这种存储器件还包括具有选择性地耦合到每个全局位线的多个局部位线的全局位线，其中每个全局位线延伸到存储器扇区的每个存储器块中的本地位线。全局位线通常成对地耦合到感测装置。通过提供具有冗余读出放大器，全局位线和局部位线的存储器单元的冗余分组来实现扇区内的一个或多个存储单元的缺陷列的修复。每组记忆体单元包含四列或更多列的存储单元。定向到包含有缺陷列的存储器单元组内的存储器单元的访问请求被重定向到存储器单元的冗余分组。因此，一列存储器单元中的缺陷导致四列或更多列存储器单元的替换。

4. 发明授权

US06304488B1 Current limiting negative switch circuit 有权
标题翻译：限流负极开关电路
公开(公告)号：US06304488B1
公开(公告)日：2001-10-16
申请号：US09649448
申请日：2000-08-25
申请人： Ebrahim Abedifard , Frankie F. Roohparvar
发明人： Ebrahim Abedifard , Frankie F. Roohparvar
IPC分类号： G11C1606
CPC分类号： H03K17/08142 , G11C16/08 , G11C16/12
摘要： Negative switch circuits are arranged to have a first electrical path coupled between an input and an output of the negative switch circuit and a second electrical path in parallel with the first electrical path for selectively isolating a load from a negative potential node. The first electrical path presents an open circuit in response to a first state of a first control signal and presents a closed circuit in response to a second state of the first control signal. The second electrical path presents an open circuit in response to either a first state of a second control signal or a condition of the load indicative of a defect associated with the load, and presents a closed circuit in response to a second state of the second control signal in combination with a condition of the load not indicative of such a defect. Such negative switch circuits are adaptable to isolate defective portions of a memory device from a negative charge pump during block erase operations. In operation, the negative switch circuit isolates the input of the negative switch circuit from the output of the negative switch circuit if a detected condition of the output of the negative switch circuit is indicative of a defect while permitting coupling of the input of the negative switch circuit to the output of the negative switch circuit if the detected condition of the output of the negative switch circuit is not indicative of a defect.
摘要翻译：负开关电路被布置为具有耦合在负开关电路的输入和输出之间的第一电路和与第一电路并联的第二电路，用于选择性地将负载与负电位节点隔离。第一电路响应于第一控制信号的第一状态而呈现开路，并且响应于第一控制信号的第二状态呈现闭合电路。第二电路响应于第二控制信号的第一状态或指示与负载相关联的缺陷的负载的条件而呈现开路，并响应于第二控制的第二状态呈现闭路信号与不指示这种缺陷的负载条件相结合。这样的负开关电路适用于在块擦除操作期间将存储器件的不良部分与负电荷泵隔离。在操作中，如果负开关电路的输出的检测条件指示缺陷，则负开关电路将负开关电路的输入与负开关电路的输出隔离，同时允许负开关的输入耦合如果负开关电路的输出的检测条件不指示缺陷，则向负开关电路的输出发送电路。

5. 发明授权

US07952924B2 NAND memory device and programming methods 有权
标题翻译： NAND存储器件和编程方法
公开(公告)号：US07952924B2
公开(公告)日：2011-05-31
申请号：US12827892
申请日：2010-06-30
申请人： Frankie F. Roohparvar , Ebrahim Abedifard
发明人： Frankie F. Roohparvar , Ebrahim Abedifard
IPC分类号： G11C11/34
CPC分类号： G11C16/0483 , G11C16/12 , G11C16/3459 , G11C2216/14
摘要： A NAND Flash memory device is described that can reduce bit line coupling and floating gate coupling during program and verify operations. Consecutive bit lines of an array row are concurrently programmed as a common page. Floating gate coupling during programming can therefore be reduced. Multiple verify operations are performed on separate bit lines of the page. Bit line coupling can therefore be reduced.
摘要翻译：描述了一种NAND闪存器件，其可以在编程和验证操作期间减少位线耦合和浮动栅极耦合。阵列行的连续位线被同时编程为公共页面。因此可以减少编程期间的浮动栅极耦合。在页面的单独位线上执行多个验证操作。因此可以减少位线耦合。

6. 发明授权

US06975538B2 Memory block erasing in a flash memory device 有权
标题翻译：闪存设备中的内存块擦除
公开(公告)号：US06975538B2
公开(公告)日：2005-12-13
申请号：US10681482
申请日：2003-10-08
申请人： Ebrahim Abedifard , Frankie F. Roohparvar
发明人： Ebrahim Abedifard , Frankie F. Roohparvar
IPC分类号： G11C11/34 , G11C16/04 , G11C16/16 , G11C16/34
CPC分类号： G11C16/345 , G11C16/16 , G11C16/3404 , G11C16/3409 , G11C16/344
摘要： An erase pulse is applied to the memory block to be erased. An erase verification operation is performed to verify that each memory cell of the memory block is erased. If a memory cell has a current less than a first sense amplifier current reference level, additional erase pulses are applied to that cell until either the erase current is in the range of 30–40 μA or a maximum quantity of erase pulses have been applied. A leakage check is performed to determine if any cells have been overerased. If a cell has an erase current greater than or equal to a second sense amplifier current reference level, soft programming pulses are applied to the cell until either its erase current is less than the second reference level or a maximum quantity of soft program pulses have been applied.
摘要翻译：擦除脉冲被施加到要擦除的存储器块。执行擦除验证操作以验证存储器块的每个存储单元被擦除。如果存储单元具有小于第一读出放大器电流参考电平的电流，则向该单元施加额外的擦除脉冲，直到擦除电流在30-40μA的范围内或者已经施加了最大量的擦除脉冲。执行泄漏检查以确定是否有任何细胞已经过度流出。如果单元具有大于或等于第二读出放大器电流参考电平的擦除电流，则将软编程脉冲施加到单元，直到其擦除电流小于第二参考电平或者最大量的软编程脉冲应用。

7. 发明授权

US06819622B2 Write and erase protection in a synchronous memory 有权
标题翻译：在同步存储器中写和擦除保护
公开(公告)号：US06819622B2
公开(公告)日：2004-11-16
申请号：US10762061
申请日：2004-01-21
申请人： Frankie F. Roohparvar , Ebrahim Abedifard
发明人： Frankie F. Roohparvar , Ebrahim Abedifard
IPC分类号： G11C700
CPC分类号： G11C16/225
摘要： A synchronous flash memory includes an array of non-volatile memory cells, and has a package configuration that is compatible with an SDRAM. The memory device includes a memory array, a programmable register circuitry to store protection data, and a voltage detector to determine if a memory power supply voltage drops below a predetermined level. Control circuitry is provided to program the register circuitry and prevent erase or write operations to the memory array in response to the voltage detector. In operation, the memory monitors a power supply voltage coupled to the memory, and prohibits write or erase operations from being performed if the supply voltage drops below a predetermined value.
摘要翻译：同步闪速存储器包括非易失性存储器单元的阵列，并具有与SDRAM兼容的封装配置。存储器件包括存储器阵列，用于存储保护数据的可编程寄存器电路和用于确定存储器电源电压是否降低到预定电平以下的电压检测器。提供控制电路以对寄存器电路进行编程，并且防止响应于电压检测器对存储器阵列的擦除或写入操作。在操作中，存储器监视耦合到存储器的电源电压，并且如果电源电压降低到预定值以下，则禁止执行写入或擦除操作。

8. 发明授权

US06396728B1 Array organization for high-performance memory devices 有权
公开(公告)号：US06396728B1
公开(公告)日：2002-05-28
申请号：US09628145
申请日：2000-07-28
申请人： Ebrahim Abedifard , Frankie F. Roohparvar
发明人： Ebrahim Abedifard , Frankie F. Roohparvar
IPC分类号： G11C506
CPC分类号： G11C16/24 , G11C16/08
摘要： Memory devices including blocks of memory cells arranged in columns, with each column of memory cells coupled to a main bit line, are organized for high-speed access and tight packing. Such memory devices include sector bit lines having multiple main bit lines selectively coupled to each sector bit line, with each sector bit line extending to main bit lines in each memory block of a memory sector. Sector bit lines are coupled to sensing devices and the output of each sensing device is selectively coupled to a global bit line, with each global bit line selectively coupled to more than one sensing device. The global bit lines are multiplexed and input to helper flip-flops for output to the data output register of the memory device. Various embodiments include non-volatile, and, particularly, synchronous non-volatile memory devices having multiple banks containing multiple sectors of such memory blocks.

9. 发明授权

US07701762B2 NAND memory device and programming methods 有权
公开(公告)号：US07701762B2
公开(公告)日：2010-04-20
申请号：US11714542
申请日：2007-03-06
申请人： Frankie F. Roohparvar , Ebrahim Abedifard
发明人： Frankie F. Roohparvar , Ebrahim Abedifard
IPC分类号： G11C11/34
CPC分类号： G11C16/0483 , G11C16/12 , G11C16/3459 , G11C2216/14
摘要： A NAND Flash memory device is described that can reduce bit line coupling and floating gate coupling during program and verify operations. Consecutive bit lines of an array row are concurrently programmed as a common page. Floating gate coupling during programming can therefore be reduced. Multiple verify operations are performed on separate bit lines of the page. Bit line coupling can therefore be reduced.

10. 发明授权

US07180781B2 Memory block erasing in a flash memory device 有权
标题翻译：闪存设备中的内存块擦除
公开(公告)号：US07180781B2
公开(公告)日：2007-02-20
申请号：US11210083
申请日：2005-08-23
申请人： Ebrahim Abedifard , Frankie F. Roohparvar
发明人： Ebrahim Abedifard , Frankie F. Roohparvar
IPC分类号： G11C16/04
CPC分类号： G11C16/345 , G11C16/16 , G11C16/3404 , G11C16/3409 , G11C16/344
摘要： An erase pulse is applied to the memory block to be erased. An erase verification operation is performed to verify that each memory cell of the memory block is erased. If a memory cell has a current less than a first sense amplifier current reference level, additional erase pulses are applied to that cell until either the erase current is in the range of 30–40 μA or a maximum quantity of erase pulses have been applied. A leakage check is performed to determine if any cells have been overerased. If a cell has an erase current greater than or equal to a second sense amplifier current reference level, soft programming pulses are applied to the cell until either its erase current is less than the second reference level or a maximum quantity of soft program pulses have been applied.
摘要翻译：擦除脉冲被施加到要擦除的存储器块。执行擦除验证操作以验证存储器块的每个存储单元被擦除。如果存储单元具有小于第一读出放大器电流参考电平的电流，则向该单元施加额外的擦除脉冲，直到擦除电流在30-40μA的范围内或者已经施加了最大量的擦除脉冲。执行泄漏检查以确定是否有任何细胞已经过度流出。如果单元具有大于或等于第二读出放大器电流参考电平的擦除电流，则将软编程脉冲施加到单元，直到其擦除电流小于第二参考电平或者最大量的软编程脉冲应用。

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