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    • 1. 发明授权
      US06890184B2 Electrical connector for conveying signals between two circuit boards 有权
    • Electrical connector for conveying signals between two circuit boards
    • 用于在两个电路板之间传送信号的电气连接器
    • US06890184B2
    • 2005-05-10
    • US10411612
    • 2003-04-10
    • Drew G. Doblar , Han Y. Ko , Stephen K. Gee
    • Drew G. Doblar , Han Y. Ko , Stephen K. Gee
    • H05K1/11 , H05K1/14 , H01R12/00
    • H05K1/14 , H01R12/52 , H05K1/11 , H05K2201/10189 , H05K2201/10734
    • An electrical connector for conveying signals between two circuit boards includes a first connector portion including a first array of board contacts for connection to a first corresponding footprint on a first circuit board. The connector also includes a second connector portion including a second array of board contacts for connection to a second corresponding footprint on a second circuit board. The signals include a plurality of signal groups each including a different plurality of related signals. Each of the signal groups is assigned to a grouping of related board contacts of the first array and to a corresponding grouping of related board contacts of the second array. When the first connector portion and the second connector portion are mated, each grouping of board contacts of the first array is electrically coupled to the corresponding grouping of board contacts in a transposed location in the second array.
    • 用于在两个电路板之间传送信号的电连接器包括第一连接器部分，其包括用于连接到第一电路板上的第一对应覆盖区的第一阵列的触点。 连接器还包括第二连接器部分，其包括用于连接到第二电路板上的第二对应覆盖区的第二阵列的触点。 信号包括多个信号组，每个信号组包括不同的多个相关信号。 每个信号组被分配给第一阵列的相关板触点的分组以及与第二阵列的相关板触点的对应分组。 当第一连接器部分和第二连接器部分配合时，第一阵列的每组基板触点在第二阵列中的转置位置中电耦合到对应的板触点组。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 2. 发明授权
      US06338144B2 Computer system providing low skew clock signals to a synchronous memory unit 有权
    • Computer system providing low skew clock signals to a synchronous memory unit
    • US06338144B2
    • 2002-01-08
    • US09252768
    • 1999-02-19
    • Drew G. Doblar , Han Y. Ko
    • Drew G. Doblar , Han Y. Ko
    • G06F104
    • G11C5/063 , G11C7/22 , G11C7/222
    • A computer system is described including a processor for executing instructions, a memory module for storing instructions and data, and a memory controller coupled between the processor and the memory module. The memory controller provides a differential clock signal and memory access signals which are routed to the memory module. The memory module includes multiple memory devices coupled to a clock buffer. The clock buffer produces a new single-ended “regenerated” clock signal from the differential clock signal. The clock buffer includes an input buffer circuit and a phase-locked loop (PLL). The input buffer circuit receives the differential clock signal from the memory controller and produces a single-ended reference clock signal from the differential clock signal. The PLL produces the regenerated clock signal substantially at the same frequency of, and in synchronization with, the single-ended reference clock signal produced by the input buffer circuit. Each of the multiple memory devices is coupled to receive the regenerated clock signal, and the operations of the multiple memory devices are synchronized to the regenerated clock signal. The multiple memory devices within the memory module may be coupled to receive the memory access signals produced by the memory controller, and may store data or retrieve data in response to the memory access signals and the regenerated clock signal. The multiple memory devices may include synchronous dynamic random access memory (SDRAM) devices, and the memory module may be a dual in-line memory module (DIMM).
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 3. 发明授权
      US06714433B2 Memory module with equal driver loading 有权
    • Memory module with equal driver loading
    • 具有相同驱动程序加载的内存模块
    • US06714433B2
    • 2004-03-30
    • US09882701
    • 2001-06-15
    • Drew G. Doblar , Han Y. Ko
    • Drew G. Doblar , Han Y. Ko
    • G11C506
    • G11C5/06 , G11C5/04 , H05K1/181
    • A memory module comprising a printed circuit board having mounting locations for a plurality of memory chips. A line driver having a plurality of outputs for each input is used to drive address and control signals to the chips, with each set of outputs coupled to a subset of the chips. Memory access time is improved by limiting subset size and thereby limiting driver loading. Subsets may correlate to banks of memory chips. Access time is substantially the same for a module with a plurality of banks of memory chips as it is for a module with only one bank of chips. Computer memory may be efficiently exchanged by using only such memory modules, allowing higher clock speed since the range of memory access times is reduced and requiring no change to system memory configuration or settings. Memory modules having differing capacities can be easily interchanged in the system.
    • 一种存储模块，包括具有用于多个存储器芯片的安装位置的印刷电路板。 具有用于每个输入的多个输出的线驱动器用于驱动地址和控制信号到芯片，每组输出耦合到芯片的子集。 通过限制子集大小从而限制驱动程序加载来提高存储器访问时间。 子集可能与存储器芯片组相关联。 具有多个存储器芯片组的模块的访问时间基本相同，因为对于仅具有一个芯片组的模块。 可以通过仅使用这样的存储器模块来有效地交换计算机存储器，从而允许更高的时钟速度，因为存储器访问时间的范围被减少并且不需要改变系统存储器配置或设置。 具有不同容量的存储器模块可以容易地在系统中互换。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 4. 发明授权
      US06640309B2 Computer system providing low skew clock signals to a synchronous memory unit 有权
    • Computer system providing low skew clock signals to a synchronous memory unit
    • US06640309B2
    • 2003-10-28
    • US10005593
    • 2001-10-26
    • Drew G. Doblar , Han Y. Ko
    • Drew G. Doblar , Han Y. Ko
    • G06F104
    • G11C5/063 , G11C7/22 , G11C7/222
    • A computer system is described including a processor for executing instructions, a memory module for storing instructions and data, and a memory controller coupled between the processor and the memory module. The memory controller provides a differential clock signal and memory access signals which are routed to the memory module. The memory module includes multiple memory devices coupled to a clock buffer. The clock buffer produces a new single-ended “regenerated” clock signal from the differential clock signal. The clock buffer includes an input buffer circuit and a phase-locked loop (PLL). The input buffer circuit receives the differential clock signal from the memory controller and produces a single-ended reference clock signal from the differential clock signal. The PLL produces the regenerated clock signal substantially at the same frequency of, and in synchronization with, the single-ended reference clock signal produced by the input buffer circuit. Each of the multiple memory devices is coupled to receive the regenerated clock signal, and the operations of the multiple memory devices are synchronized to the regenerated clock signal. The multiple memory devices within the memory module may be coupled to receive the memory access signals produced by the memory controller, and may store data or retrieve data in response to the memory access signals and the regenerated clock signal. The multiple memory devices may include synchronous dynamic random access memory (SDRAM) devices, and the memory module may be a dual in-line memory module (DIMM).
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 7. 发明授权
      US06751740B1 Method and system for using a combined power detect and presence detect signal to determine if a memory module is connected and receiving power 失效
    • Method and system for using a combined power detect and presence detect signal to determine if a memory module is connected and receiving power
    • 使用组合的功率检测和存在检测信号来确定存储器模块是否连接并接收功率的方法和系统
    • US06751740B1
    • 2004-06-15
    • US09638050
    • 2000-08-11
    • William L. Robertson , Han Y. Ko
    • William L. Robertson , Han Y. Ko
    • G06F128
    • G11C5/143
    • A system and method for providing a common power detect and presence detect signal. In one embodiment, a memory module includes a voltage regulator and a power detector circuit. The voltage regulator may be configured to provide a stable operating voltage to the various circuits of the memory module. The power detector circuit may be configured to detect the presence of the operating voltage from the output of the voltage regulator. The power detector circuit may assert an output signal in response to a detection of a voltage from the voltage regulator. The output signal asserted by the power detector circuit may then be driven through a single pin of a connector mounted to the memory module to a storage unit of the host computer system. The storage unit may be configured to store the state of the output signal. Instructions executed by a central processing unit (CPU) of the computer system may cause the state of the output signal to be periodically read from the storage unit, and provide an indication as to whether the voltage regulator is providing the operating voltage. If the memory module is not receiving the correct operating voltage, or it is not present, an indication of this condition may be provided to a user of the computer system.
    • 一种用于提供公共功率检测和存在检测信号的系统和方法。 在一个实施例中，存储器模块包括电压调节器和功率检测器电路。 电压调节器可以被配置为向存储器模块的各种电路提供稳定的工作电压。 功率检测器电路可以被配置为从电压调节器的输出检测工作电压的存在。 功率检测器电路可以响应于来自电压调节器的电压的检测而断言输出信号。 然后，由功率检测器电路确定的输出信号可以通过安装到存储器模块的连接器的单个引脚驱动到主计算机系统的存储单元。 存储单元可以被配置为存储输出信号的状态。 由计算机系统的中央处理单元（CPU）执行的指令可以使得输出信号的状态从存储单元周期性地读取，并提供关于电压调节器是否提供工作电压的指示。 如果存储器模块没有接收到正确的操作电压，或者它不存在，则可以向计算机系统的用户提供该状况的指示。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 8. 发明授权
      US06534872B1 Apparatus and system with increased signal trace routing options in printed wiring boards and integrated circuit packaging 有权
    • Apparatus and system with increased signal trace routing options in printed wiring boards and integrated circuit packaging
    • 装置和系统在印刷电路板和集成电路封装中增加了信号跟踪布线选项
    • US06534872B1
    • 2003-03-18
    • US09371722
    • 1999-08-10
    • Michael C. Freda , Han Y. Ko , Ali Hassanzadeh
    • Michael C. Freda , Han Y. Ko , Ali Hassanzadeh
    • H01L2940
    • H05K1/114 , H01L2924/15174 , H05K1/113 , H05K1/115 , H05K3/4644 , H05K2201/09227 , H05K2201/09627 , H05K2201/10734
    • An apparatus and system comprising electrical interconnection devices (EIDs), such as printed wiring boards, semiconductor packages, and printed circuit boards, having novel via and signal trace positioning. The vias may be positioned off-center from the pattern of the surface pads. Via groups, or staircase vias, connect surface pads with vias extending into the electrical interconnection device. The via groups convert the pad geometry on the surface to a more open via pattern on one or more internal layers. The EID comprises a plurality of pads formed on a surface for providing electrical connections to another EID. A plurality of vias each extend from a corresponding pad to another layer of the printed wiring board. Each via is offset from a central location of its corresponding pad. A via group comprises a plurality of vias with a first via connecting a surface of the electrical interconnection device to a first inner layer electrically connects a pad on a surface of the electrical interconnection device to a second via. The second via extends from the first inner layer to a second layer of the electrical interconnection device. The centers of the first via and the second via are non-collinear. Another EID includes a uniformly spaced set of pads on the surface. Via groups, comprising a first set of vias and a second set of vias, extend from the uniformly spaced surface pads. Spacing among the second set of vias is non-uniform.
    • 包括具有新颖的通孔和信号迹线定位的电互连装置（EID），例如印刷电路板，半导体封装和印刷电路板的装置和系统。 通孔可以离开表面焊盘的图案偏离中心。 通过组或楼梯通孔，将表面焊盘连接到延伸到电互连装置中的通孔。 通孔组将表面上的焊盘几何形状转换为一个或多个内部层上的更开放的通孔图案。 EID包括形成在表面上的多个焊盘，用于提供与另一EID的电连接。 多个通孔各自从相应的垫延伸到印刷线路板的另一层。 每个通孔偏离其对应的垫的中心位置。 通孔组包括多个通孔，第一通孔将电互连装置的表面连接到第一内层，将电互连装置的表面上的焊盘电连接到第二通孔。 第二通孔从电互连装置的第一内层延伸到第二层。 第一通孔和第二通孔的中心是非共线的。 另一个EID包括表面上均匀间隔的一组垫。 包括第一组通孔和第二组通孔的通孔组从均匀间隔的表面焊盘延伸。 第二组通道之间的间距是不均匀的。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
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