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    • 10. 发明授权
    • Enhanced rake structure
    • 增强耙结构
    • US06771693B2
    • 2004-08-03
    • US10034874
    • 2001-12-27
    • William C. Hackett
    • William C. Hackett
    • H04B169
    • H04B1/7117H04B2201/70707
    • A rake architecture for a frequency division duplex (FDD) and use also in TDD and TD-SCDMA type communications system, designed to significantly reduce the memory capacity required and thereby also reduce an area on the die of an application specific integrated circuit (ASIC) into which the memory is integrated. A single circular buffer, preferably of the shared memory type is shared by all of the rake fingers of a rake receiver to significantly reduce the hardware and software required to time align multipath signals received by a UE from a base station. This unique time alignment technique also reduces the number of code generators required to track a plurality (typically three) of base stations.
    • 用于频分双工(FDD)的耙式架构,并且还用于TDD和TD-SCDMA型通信系统,旨在显着地减少所需的存储器容量,从而也减少专用集成电路(ASIC)的芯片上的面积, 内存被集成到其中。 优选共享存储器类型的单个循环缓冲器由耙式接收器的所有耙指共享,以显着地减少时间校准由UE从基站接收的多路径信号所需的硬件和软件。 这种独特的时间对准技术还减少了跟踪多个(通常为三个)基站所需的代码生成器的数量。