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    • 3. 发明申请
    • Lockable fastener and circuit breaker employing the same
    • 可锁紧紧固件和采用该紧固件的断路器
    • US20060071745A1
    • 2006-04-06
    • US10958172
    • 2004-10-01
    • Amelia StayDavid ParksDavid LittleDavid Groves
    • Amelia StayDavid ParksDavid LittleDavid Groves
    • H01H9/00
    • H01H1/5833F16B39/025H01H71/0207
    • A lockable fastener connects together a plurality of components of a circuit breaker and maintains electrical conductivity between the components while permitting relative movement therebetween. The lockable fastener includes a first clinch nut member and a second clinch bolt member. The clinch nut member includes a threaded cavity formed therein, a side having opening therein, and a passageway between the side at the opening and a surface proximate the threaded cavity. The clinch bolt member includes a threaded shank. At least a portion of the threaded shank is threadably receivable in the threaded cavity of the clinch nut member, in order to axially align the clinch nut and clinch bolt members. The clinch nut and clinch bolt members are adapted to be locked by deformation of the surface of the clinch nut member to prevent loosening of the members.
    • 可锁定紧固件将断路器的多个部件连接在一起,并且保持部件之间的导电性,同时允许它们之间的相对移动。 可锁定紧固件包括第一紧固螺母构件和第二搭扣螺栓构件。 夹紧螺母构件包括形成在其中的螺纹空腔,其中具有开口的侧面以及在开口侧面和靠近螺纹空腔的表面之间的通道。 夹紧螺栓构件包括螺纹柄。 螺纹杆的至少一部分可螺纹地容纳在夹紧螺母构件的螺纹空腔中,以便使夹紧螺母和夹紧螺栓构件轴向对准。 夹紧螺母和夹紧螺栓构件适于通过夹紧螺母构件的表面变形来锁定,以防止构件松动。
    • 7. 发明授权
    • System and method for semaphore and atomic operation management in a multiprocessor
    • 多处理器中信号量和原子操作管理的系统和方法
    • US06594736B1
    • 2003-07-15
    • US09638365
    • 2000-08-15
    • David Parks
    • David Parks
    • G06F1200
    • G06F15/17375G06F12/0815
    • A method and apparatus including a plurality of data processing units. A plurality of memory banks having a shared address space are coupled to the processors by a crossbar coupling to enable reading and writing data between the processors and memory banks. A unidirectional network couples the memory banks and the processors to enable cache coherency messages to be transmitted from the memory to the processors. A plurality of semaphore registers are implemented within the shared address space of the memory banks wherein the semaphore registers are accessible by the processors through the crossbar coupling.
    • 一种包括多个数据处理单元的方法和装置。 具有共享地址空间的多个存储体通过交叉耦合耦合到处理器,以使得能够在处理器和存储体之间读取和写入数据。 单向网络耦合存储体和处理器以使高速缓存一致性消息能够从存储器传送到处理器。 在存储器组的共享地址空间内实现多个信号量寄存器,其中信号量寄存器可由处理器通过交叉耦合来访问。
    • 8. 发明授权
    • Systems and methods for pseudowire-in-pseudowire to transport pseudowire payload across packet switched networks
    • 用于在分组交换网络中传输伪线有效载荷的伪线伪线的系统和方法
    • US08295278B2
    • 2012-10-23
    • US11958656
    • 2007-12-18
    • Himanshu ShahMark LibbyDavid Parks
    • Himanshu ShahMark LibbyDavid Parks
    • H04L12/28
    • H04L12/4633
    • The present invention provides systems and methods which create an infrastructure/transport Pseudowire (PW) a priori between two Provider Edge (PE) devices. Accordingly, other PWs can be mapped to this transport PW. In an exemplary application, the transport PW (which is a MS-PW by itself) can start and end between two Switching Provider Edge (S-PE) devices and span across multiple S-PEs in between. In another exemplary application, the transport PW terminates between two Terminating Provider Edge (T-PE) devices spanning across all S-PEs in between. In a further exemplary application, the transport PW can start at a S-PE or T-PE and terminate at a T-PE or S-PE, respectively. The placement of the endpoints of the transport PW (on two PEs) determines the number of intervening S-PEs that benefit from this application.
    • 本发明提供了在两个提供商边缘(PE)设备之间先验地创建基础设施/传输伪线(PW)的系统和方法。 因此,可以将其他PW映射到该传输PW。 在示例性应用中,传输PW(其自身是MS-PW)可以在两个交换提供商边缘(S-PE)设备之间开始和结束,跨越多个S-PE之间。 在另一示例性应用中,传输PW终止于跨越其间的所有S-PE的两个终端提供商边缘(T-PE)设备。 在另一示例性应用中,传输PW可以在S-PE或T-PE上启动并分别终止在T-PE或S-PE。 传输PW的端点(在两个PE上)的位置决定了受益于该应用的中间S-PE的数量。