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1. 发明授权

US07890694B2 Latched address multi-chunk write to EEPROM 有权
标题翻译：锁存地址多块写入EEPROM
公开(公告)号：US07890694B2
公开(公告)日：2011-02-15
申请号：US12469531
申请日：2009-05-20
申请人： Douglas J. Lee , Mehrdad Mofidi , Sanjay Mehrotra , Raul-Adrian Cernea
发明人： Douglas J. Lee , Mehrdad Mofidi , Sanjay Mehrotra , Raul-Adrian Cernea
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G11C16/08 , G11C8/12 , G11C16/10
摘要： An EEPROM system includes flash EEPROM cells organized into subarrays. Pairs of subarrays share row address decoders by sharing word lines, and individual subarrays have dedicated column address decoders and data registers. Each row decoder has an associated row address latch, and each column decoder has an associated column address latch. Multiple data chunks are concurrently written into the subarrays by first latching chunk addresses into the row and column address latches, and corresponding chunks of data into the data registers, then activating a programming signal to initiate concurrent programming and verifying the programming of the data chunks.
摘要翻译： EEPROM系统包括组织成子阵列的闪存EEPROM单元。一对子阵列通过共享字线共享行地址解码器，并且单个子阵列具有专用列地址解码器和数据寄存器。每行解码器具有相关联的行地址锁存器，并且每个列解码器具有相关联的列地址锁存器。通过首先将块地址锁存到行和列地址锁存器中，并将相应的数据块块数据写入数据寄存器中，然后激活编程信号以启动并行编程并验证数据块的编程，将多个数据块同时写入子阵列。

2. 发明授权

US5592420A Programmable power generation circuit for flash EEPROM memory systems 失效
公开(公告)号：US5592420A
公开(公告)日：1997-01-07
申请号：US482939
申请日：1995-06-07
申请人： Raul-Adrian Cernea , Douglas J. Lee , Mehrdad Mofidi , Sanjay Mehrotra
发明人： Raul-Adrian Cernea , Douglas J. Lee , Mehrdad Mofidi , Sanjay Mehrotra
IPC分类号： G11C16/16 , G11C16/30 , G11C11/34
CPC分类号： G11C16/30 , G11C16/16
摘要： An flash EEPROM system functioning as a mass storage medium for a host computer includes a controller and at least one flash EEPROM memory module. The flash EEPROM memory module includes at least one flash EEPROM chip having an on-chip programmable power generation circuit including a high voltage generator circuit capable of generating a high voltage Vpp from a logic level voltage Vdd provided to the chip, a serial protocol logic circuit, a data latch, a data bus, a register address decoder, and a multi-voltage generator/regulator. The multi-voltage generator/regulator includes a plurality of registers and provides the programming, reading, and erasing voltages required for proper operation of the flash EEPROM system from digital values stored in the plurality of registers by the controller. The high voltage generator circuit includes both high current and low current charge pump circuits for generating the high voltage Vpp. The high current charge pump circuit is connected to relatively large off-chip charge storage devices, and the low current charge pump circuit is connected to relatively small on-chip charge storage devices. The controller may activate one or the other of the high or low current charge pump circuits through control signals connected to enabling circuitry respectively connected to the high and low current charge pump circuits. Alternatively, the controller may deactivate both the high and low current charge pump circuits and cause the high voltage Vpp to be provided from other circuitry on another flash EEPROM chip in the flash EEPROM module.

3. 发明授权

US5508971A Programmable power generation circuit for flash EEPROM memory systems 失效
标题翻译：用于闪存EEPROM存储器系统的可编程发电电路
公开(公告)号：US5508971A
公开(公告)日：1996-04-16
申请号：US325774
申请日：1994-10-17
申请人： Raul-Adrian Cernea , Douglas J. Lee , Mehrdad Mofidi , Sanjay Mehrotra
发明人： Raul-Adrian Cernea , Douglas J. Lee , Mehrdad Mofidi , Sanjay Mehrotra
IPC分类号： G11C16/16 , G11C16/30 , G11C7/00 , G11C11/34
CPC分类号： G11C16/30 , G11C16/16
摘要： An flash EEPROM system functioning as a mass storage medium for a host computer includes a controller and at least one flash EEPROM memory module. The flash EEPROM memory module includes at least one flash EEPROM chip having an on-chip programmable power generation circuit including a high voltage generator circuit capable of generating a high voltage Vpp from a logic level voltage Vdd provided to the chip, a serial protocol logic circuit, a data latch, a data bus, a register address decoder, and a multi-voltage generator/regulator. The multi-voltage generator/regulator includes a plurality of registers and provides the programming, reading, and erasing voltages required for proper operation of the flash EEPROM system from digital values stored in the plurality of registers by the controller. The high voltage generator circuit includes both high current and low current charge pump circuits for generating the high voltage Vpp. The high current charge pump circuit is connected to relatively large off-chip charge storage devices, and the low current charge pump circuit is connected to relatively small on-chip charge storage devices. The controller may activate one or the other of the high or low current charge pump circuits through control signals connected to enabling circuitry respectively connected to the high and low current charge pump circuits. Alternatively, the controller may deactivate both the high and low current charge pump circuits and cause the high voltage Vpp to be provided from other circuitry on another flash EEPROM chip in the flash EEPROM module.
摘要翻译：用作主计算机的大容量存储介质的快闪EEPROM系统包括控制器和至少一个闪存EEPROM存储器模块。闪存EEPROM存储器模块包括至少一个具有片上可编程发电电路的闪存EEPROM芯片，该芯片可编程发电电路包括能够从提供给芯片的逻辑电平Vdd产生高电压Vpp的高压发生器电路，串行协议逻辑电路，数据锁存器，数据总线，寄存器地址解码器和多电压发生器/调节器。多电压发生器/调节器包括多个寄存器，并且通过控制器从存储在多个寄存器中的数字值提供快速EEPROM系统的正确操作所需的编程，读取和擦除电压。高电压发生器电路包括用于产生高电压Vpp的高电流和低电流电荷泵电路。高电流电荷泵电路连接到相对较大的片外电荷存储器件，低电流电荷泵电路连接到较小的片上电荷存储器件。控制器可以通过连接到分别连接到高电流和低电流电荷泵电路的使能电路的控制信号激活高电流或低电流电荷泵电路中的一个或另一个。或者，控制器可以去激活高电流和低电流电荷泵电路，并使高电压Vpp从快闪EEPROM模块中的另一快闪EEPROM芯片上的其它电路提供。

4. 发明授权

US6157983A Concurrent write of multiple chunks of data into multiple subarrays of flash EEPROM 失效
标题翻译：将多个数据块并行写入闪存EEPROM的多个子阵列
公开(公告)号：US6157983A
公开(公告)日：2000-12-05
申请号：US226405
申请日：1999-01-06
申请人： Douglas J. Lee , Mehrdad Mofidi , Sanjay Mehrotra , Raul-Adrian Cernea
发明人： Douglas J. Lee , Mehrdad Mofidi , Sanjay Mehrotra , Raul-Adrian Cernea
IPC分类号： G11C8/12 , G11C16/08 , G11C16/10 , G06F12/00
CPC分类号： G11C16/08 , G11C16/10 , G11C8/12
摘要： An EEPROM system includes flash EEPROM cells organized into subarrays. Pairs of subarrays share row address decoders by sharing word lines, and individual subarrays have dedicated column address decoders and data registers. Each row decoder has an associated row address latch, and each column decoder has an associated column address latch. Multiple data chunks are concurrently written into the subarrays by first latching chunk addresses into the row and column address latches, and corresponding chunks of data into the data registers, then activating a programming signal to initiate concurrent programming and verifying the programming of the data chunks.
摘要翻译： EEPROM系统包括组织成子阵列的闪存EEPROM单元。一对子阵列通过共享字线共享行地址解码器，并且单个子阵列具有专用列地址解码器和数据寄存器。每行解码器具有相关联的行地址锁存器，并且每个列解码器具有相关联的列地址锁存器。通过首先将块地址锁存到行和列地址锁存器中，并将相应的数据块块数据写入数据寄存器中，然后激活编程信号以启动并行编程并验证数据块的编程，将多个数据块同时写入子阵列。

5. 发明授权

US5596532A Flash EEPROM self-adaptive voltage generation circuit operative within a continuous voltage source range 失效
标题翻译：闪存EEPROM自适应电压产生电路在连续电压源范围内工作
公开(公告)号：US5596532A
公开(公告)日：1997-01-21
申请号：US544456
申请日：1995-10-18
申请人： Raul-Adrian Cernea , Douglas J. Lee , Mehrdad Mofidi , Sanjay Mehrotra
发明人： Raul-Adrian Cernea , Douglas J. Lee , Mehrdad Mofidi , Sanjay Mehrotra
IPC分类号： G11C5/14 , G11C16/30 , G11C16/00
CPC分类号： G11C16/30 , G11C5/145
摘要： An EEPROM system operative within a continuous source voltage range includes a controller having a processor and a memory, and an EEPROM module connected to the controller and including a plurality of EEPROM chips. A representative one of the EEPROM chips includes a comparator, a programmable voltage generator, and a regulated charge pump circuit. The comparator compares a source voltage provided to the EEPROM system against one or more reference voltages indicative of subranges within the operative source voltage range, to generate one or more control signals indicative of the subrange within which the source voltage resides. The regulated charge pump circuit generates from the source voltage, a regulated high voltage output which is substantially unaffected by changes in the source voltage. Included in the regulated charge pump circuit are a feedback circuit, and an open loop gain adjustment circuit which is responsive to the the one or more control signals generated by the comparator. The programmable voltage generator is programmed by the controller to generate a plurality of specified voltages for programming, reading, and erasing selected EEPROM cells in the EEPROM chip. To adjust for changes in the source voltage provided to the EEPROM system, the controller requests the one or more control signals generated from the comparator, and modifies values programmed into the programmable voltage generator accordingly.
摘要翻译：在连续源电压范围内工作的EEPROM系统包括具有处理器和存储器的控制器以及连接到控制器并包括多个EEPROM芯片的EEPROM模块。一个代表性的EEPROM芯片包括比较器，可编程电压发生器和调节的电荷泵电路。比较器将提供给EEPROM系统的源电压与指示在操作源电压范围内的子范围的一个或多个参考电压进行比较，以产生指示源电压驻留在其中的子范围的一个或多个控制信号。调节的电荷泵电路从源极电压产生稳定的高电压输出，其基本上不受源极电压的变化的影响。包括在调节电荷泵电路中的是反馈电路和响应于由比较器产生的一个或多个控制信号的开环增益调整电路。可编程电压发生器由控制器编程以产生多个指定电压，用于对EEPROM芯片中的选定EEPROM单元进行编程，读取和擦除。为了调整提供给EEPROM系统的电源电压的变化，控制器请求从比较器产生的一个或多个控制信号，并相应地修改编程到可编程电压发生器中的值。

6. 发明授权

US5568424A Programmable power generation circuit for flash EEPROM memory systems 失效
公开(公告)号：US5568424A
公开(公告)日：1996-10-22
申请号：US478268
申请日：1995-06-07
申请人： Raul-Adrian Cernea , Douglas J. Lee , Mehrdad Mofidi , Sanjay Mehrotra
发明人： Raul-Adrian Cernea , Douglas J. Lee , Mehrdad Mofidi , Sanjay Mehrotra
IPC分类号： G11C16/16 , G11C16/30 , G11C11/34
CPC分类号： G11C16/30 , G11C16/16
摘要： An flash EEPROM system functioning as a mass storage medium for a host computer includes a controller and at least one flash EEPROM memory module. The flash EEPROM memory module includes at least one flash EEPROM chip having an on-chip programmable power generation circuit including a high voltage generator circuit capable of generating a high voltage Vpp from a logic level voltage Vdd provided to the chip, a serial protocol logic circuit, a data latch, a data bus, a register address decoder, and a multi-voltage generator/regulator. The multi-voltage generator/regulator includes a plurality of registers and provides the programming, reading, and erasing voltages required for proper operation of the flash EEPROM system from digital values stored in the plurality of registers by the controller. The high voltage generator circuit includes both high current and low current charge pump circuits for generating the high voltage Vpp. The high current charge pump circuit is connected to relatively large off-chip charge storage devices, and the low current charge pump circuit is connected to relatively small on-chip charge storage devices. The controller may activate one or the other of the high or low current charge pump circuits through control signals connected to enabling circuitry respectively connected to the high and low current charge pump circuits. Alternatively, the controller may deactivate both the high and low current charge pump circuits and cause the high voltage Vpp to be provided from other circuitry on another flash EEPROM chip in the flash EEPROM module.

7. 发明授权

US5890192A Concurrent write of multiple chunks of data into multiple subarrays of flash EEPROM 失效
公开(公告)号：US5890192A
公开(公告)日：1999-03-30
申请号：US743857
申请日：1996-11-05
申请人： Douglas J. Lee , Mehrdad Mofidi , Sanjay Mehrotra , Raul-Adrian Cernea
发明人： Douglas J. Lee , Mehrdad Mofidi , Sanjay Mehrotra , Raul-Adrian Cernea
IPC分类号： G11C8/12 , G11C16/08 , G11C16/10 , G06F13/00 , G11C16/00
CPC分类号： G11C16/08 , G11C16/10 , G11C8/12
摘要： An EEPROM system includes flash EEPROM cells organized into subarrays. Pairs of subarrays share row address decoders by sharing word lines, and individual subarrays have dedicated column address decoders and data registers. Each row decoder has an associated row address latch, and each column decoder has an associated column address latch. Multiple data chunks are concurrently written into the subarrays by first latching chunk addresses into the row and column address latches, and corresponding chunks of data into the data registers, then activating a programming signal to initiate concurrent programming and verifying the programming of the data chunks.

8. 发明授权

US5621685A Programmable power generation circuit for flash EEPROM memory systems 失效
标题翻译：用于闪存EEPROM存储器系统的可编程发电电路
公开(公告)号：US5621685A
公开(公告)日：1997-04-15
申请号：US484991
申请日：1995-06-07
申请人： Raul-Adrian Cernea , Douglas J. Lee , Mehrdad Mofidi , Sanjay Mehrotra
发明人： Raul-Adrian Cernea , Douglas J. Lee , Mehrdad Mofidi , Sanjay Mehrotra
IPC分类号： G11C16/16 , G11C16/30 , G11C11/34
CPC分类号： G11C16/30 , G11C16/16
摘要： An flash EEPROM system functioning as a mass storage medium for a host computer includes a controller and at least one flash EEPROM memory module. The flash EEPROM memory module includes at least one flash EEPROM chip having an on-chip programmable power generation circuit including a high voltage generator circuit capable of generating a high voltage Vpp from a logic level voltage Vdd provided to the chip, a serial protocol logic circuit, a data latch, a data bus, a register address decoder, and a multi-voltage generator/regulator. The multi-voltage generator/regulator includes a plurality of registers and provides the programming, reading, and erasing voltages required for proper operation of the flash EEPROM system from digital values stored in the plurality of registers by the controller. The high voltage generator circuit includes both high current and low current charge pump circuits for generating the high voltage Vpp. The high current charge pump circuit is connected to relatively large off-chip charge storage devices, and the low current charge pump circuit is connected to relatively small on-chip charge storage devices. The controller may activate one or the other of the high or low current charge pump circuits through control signals connected to enabling circuitry respectively connected to the high and low current charge pump circuits. Alternatively, the controller may deactivate both the high and low current charge pump circuits and cause the high voltage Vpp to be provided from other circuitry on another flash EEPROM chip in the flash EEPROM module.
摘要翻译：用作主计算机的大容量存储介质的快闪EEPROM系统包括控制器和至少一个闪存EEPROM存储器模块。闪存EEPROM存储器模块包括至少一个具有片上可编程发电电路的闪存EEPROM芯片，该芯片可编程发电电路包括能够从提供给芯片的逻辑电平Vdd产生高电压Vpp的高压发生器电路，串行协议逻辑电路，数据锁存器，数据总线，寄存器地址解码器和多电压发生器/调节器。多电压发生器/调节器包括多个寄存器，并且通过控制器从存储在多个寄存器中的数字值提供快速EEPROM系统的正确操作所需的编程，读取和擦除电压。高电压发生器电路包括用于产生高电压Vpp的高电流和低电流电荷泵电路。高电流电荷泵电路连接到相对较大的片外电荷存储器件，低电流电荷泵电路连接到较小的片上电荷存储器件。控制器可以通过连接到分别连接到高电流和低电流电荷泵电路的使能电路的控制信号激活高电流或低电流电荷泵电路中的一个或另一个。或者，控制器可以去激活高电流和低电流电荷泵电路，并使高电压Vpp从快闪EEPROM模块中的另一快闪EEPROM芯片上的其它电路提供。

9. 发明申请

US20090228644A1 Latched Address Multi-Chunk Write to EEPROM 有权
标题翻译：锁存地址多块写入EEPROM
公开(公告)号：US20090228644A1
公开(公告)日：2009-09-10
申请号：US12469531
申请日：2009-05-20
申请人： Douglas J. Lee , Mehrdad Mofidi , Sanjay Mehrotra , Raul-Adrian Cernea
发明人： Douglas J. Lee , Mehrdad Mofidi , Sanjay Mehrotra , Raul-Adrian Cernea
IPC分类号： G06F12/02 , G06F12/00
CPC分类号： G11C16/08 , G11C8/12 , G11C16/10
摘要： An EEPROM system includes flash EEPROM cells organized into subarrays. Pairs of subarrays share row address decoders by sharing word lines, and individual subarrays have dedicated column address decoders and data registers. Each row decoder has an associated row address latch, and each column decoder has an associated column address latch. Multiple data chunks are concurrently written into the subarrays by first latching chunk addresses into the row and column address latches, and corresponding chunks of data into the data registers, then activating a programming signal to initiate concurrent programming and verifying the programming of the data chunks.
摘要翻译： EEPROM系统包括组织成子阵列的闪存EEPROM单元。一对子阵列通过共享字线共享行地址解码器，并且单个子阵列具有专用列地址解码器和数据寄存器。每行解码器具有相关联的行地址锁存器，并且每个列解码器具有相关联的列地址锁存器。通过首先将块地址锁存到行和列地址锁存器中，并将相应的数据块块数据写入数据寄存器中，然后激活编程信号以启动并行编程并验证数据块的编程，将多个数据块同时写入子阵列。

10. 发明授权

US06829673B2 Latched address multi-chunk write to EEPROM 失效
标题翻译：锁存地址多块写入EEPROM
公开(公告)号：US06829673B2
公开(公告)日：2004-12-07
申请号：US10286078
申请日：2002-11-01
申请人： Douglas J. Lee , Mehrdad Mofidi , Sanjay Mehrotra , Raul-Adrian Cernea
发明人： Douglas J. Lee , Mehrdad Mofidi , Sanjay Mehrotra , Raul-Adrian Cernea
IPC分类号： G06F1200
CPC分类号： G11C16/08 , G11C8/12 , G11C16/10
摘要： An EEPROM system includes flash EEPROM cells organized into subarrays. Pairs of subarrays share row address decoders by sharing word lines, and individual subarrays have dedicated column address decoders and data registers. Each row decoder has an associated row address latch, and each column decoder has an associated column address latch. Multiple data chunks are concurrently written into the subarrays by first latching chunk addresses into the row and column address latches, and corresponding chunks of data into the data registers, then activating a programming signal to initiate concurrent programming and verifying the programming of the data chunks.
摘要翻译： EEPROM系统包括组织成子阵列的闪存EEPROM单元。一对子阵列通过共享字线共享行地址解码器，并且单个子阵列具有专用列地址解码器和数据寄存器。每行解码器具有相关联的行地址锁存器，并且每个列解码器具有相关联的列地址锁存器。通过首先将块地址锁存到行和列地址锁存器中，并将相应的数据块块数据写入数据寄存器中，然后激活编程信号以启动并行编程并验证数据块的编程，将多个数据块同时写入子阵列。

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