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1. 发明授权

US5982656A Method and apparatus for checking the resistance of programmable elements 失效
标题翻译：用于检查可编程元件电阻的方法和装置
公开(公告)号：US5982656A
公开(公告)日：1999-11-09
申请号：US813767
申请日：1997-03-07
申请人： Douglas J. Cutter , Fan Ho , Kurt D. Beigel , Brett M. Debenham , Dien Luong , Kim Pierce , Patrick J. Mullarkey
发明人： Douglas J. Cutter , Fan Ho , Kurt D. Beigel , Brett M. Debenham , Dien Luong , Kim Pierce , Patrick J. Mullarkey
IPC分类号： G11C17/16 , G11C29/02 , G11C17/00
CPC分类号： G11C29/02 , G11C17/16
摘要： Method and apparatus are disclosed for checking the resistance of programmable circuits in an integrated circuit where each programmable circuit includes a programmable element, such as an antifuse. A precharged node is connected to the programmable element and the voltage at the node discharges based on the resistance of the programmable element. An output signal is produced whose binary value is based on the voltage at the node after a sufficient time has elapsed to allow the initial voltage to discharge based on the resistance of the programmable element.
摘要翻译：公开了用于检查集成电路中的可编程电路的电阻的方法和装置，其中每个可编程电路包括诸如反熔丝的可编程元件。预充电节点连接到可编程元件，并且节点处的电压基于可编程元件的电阻而放电。产生输出信号，其二进制值基于经过足够时间之后的节点处的电压，以允许初始电压基于可编程元件的电阻放电。

2. 发明授权

US06185705B2 Method and apparatus for checking the resistance of programmable elements 失效
标题翻译：用于检查可编程元件电阻的方法和装置
公开(公告)号：US06185705B2
公开(公告)日：2001-02-06
申请号：US08813525
申请日：1997-03-07
申请人： Douglas J. Cutter , Adrian E. Ong , Fan Ho , Kurt D. Beigel , Brett M. Debenham , Dien Luong , Kim Pierce , Patrick J. Mullarkey
发明人： Douglas J. Cutter , Adrian E. Ong , Fan Ho , Kurt D. Beigel , Brett M. Debenham , Dien Luong , Kim Pierce , Patrick J. Mullarkey
IPC分类号： G11C2900
CPC分类号： G11C17/18
摘要： Method and apparatus are disclosed for checking the resistance of antifuse elements in an integrated circuit. A voltage based on the resistance of an antifuse element is compared to a voltage based on a known resistance, and an output signal is generated whose binary value indicates whether the resistance of the antifuse element is higher or lower than the known value of resistance. The method and apparatus are useful in verifying the programming of antifuse elements.
摘要翻译：公开了用于检查集成电路中的反熔丝元件的电阻的方法和装置。将基于反熔丝元件的电阻的电压与基于已知电阻的电压进行比较，并且生成其二进制值表示反熔丝元件的电阻是否高于或低于已知电阻值的输出信号。该方法和装置在验证反熔丝元件的编程方面是有用的。

3. 发明授权

US06983404B2 Method and apparatus for checking the resistance of programmable elements 失效
标题翻译：用于检查可编程元件电阻的方法和装置
公开(公告)号：US06983404B2
公开(公告)日：2006-01-03
申请号：US09777036
申请日：2001-02-05
申请人： Douglas J. Cutter , Adrian E. Ong , Fan Ho , Kurt D. Beigel , Brett M. Debenham , Dien Luong , Kim Pierce , Patrick J. Mullarkey
发明人： Douglas J. Cutter , Adrian E. Ong , Fan Ho , Kurt D. Beigel , Brett M. Debenham , Dien Luong , Kim Pierce , Patrick J. Mullarkey
IPC分类号： G11C29/00
CPC分类号： G11C17/18
摘要： Method and apparatus are disclosed for checking the resistance of antifuse elements in an integrated circuit. A voltage based on the resistance of an antifuse element is compared to a voltage based on a known resistance, and an output signal is generated whose binary value indicates whether the resistance of the antifuse element is higher or lower than the known value of resistance. The method and apparatus are useful in verifying the programming of antifuse elements.
摘要翻译：公开了用于检查集成电路中的反熔丝元件的电阻的方法和装置。将基于反熔丝元件的电阻的电压与基于已知电阻的电压进行比较，并且生成其二进制值表示反熔丝元件的电阻是否高于或低于已知电阻值的输出信号。该方法和装置在验证反熔丝元件的编程方面是有用的。

4. 发明授权

US07237158B2 Intelligent binning for electrically repairable semiconductor chips 失效
标题翻译：用于电可修复半导体芯片的智能合并
公开(公告)号：US07237158B2
公开(公告)日：2007-06-26
申请号：US10608798
申请日：2003-06-26
申请人： Brett M. Debenham
发明人： Brett M. Debenham
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G01R31/01 , G01R31/2851 , G01R31/31718 , G01R31/319 , G11C29/44 , G11C29/56
摘要： The present invention relates to a system and method for testing one or more semiconductor devices (e.g., packaged chips). Test equipment performs at least tests of a first type on the semiconductor device and identifies failures in the semiconductor device, if any. A number of failures are determined. In the case where there are some failures, decision circuitry determines whether it is more efficient to repeat the tests or repair the semiconductor device, if it is repairable.
摘要翻译：本发明涉及用于测试一个或多个半导体器件（例如封装芯片）的系统和方法。测试设备至少执行半导体器件上的第一类测试，并识别半导体器件中的故障（如果有的话）。确定了一些故障。在存在某些故障的情况下，决定电路确定重复测试或修复半导体器件是否更有效，如果它是可修复的。

5. 发明授权

US06219810B1 Intelligent binning for electrically repairable semiconductor chips 有权
标题翻译：用于电可修复半导体芯片的智能合并
公开(公告)号：US06219810B1
公开(公告)日：2001-04-17
申请号：US09523579
申请日：2000-03-10
申请人： Brett M. Debenham
发明人： Brett M. Debenham
IPC分类号： G06F1100
CPC分类号： G01R31/01 , G01R31/2851 , G01R31/31718 , G01R31/319 , G11C29/44 , G11C29/56
摘要： The present invention relates to a system and method for testing one or more semiconductor devices (e.g., packaged chips). Test equipment performs at least tests of a first type on the semiconductor device and identifies failures in the semiconductor device, if any. A number of failures is determined. In the case where there are some failures, decision circuitry determines whether it is more efficient to repeat the tests or repair the semiconductor device, if it is repairable. The semiconductor device may be binned differently depending on the number of identified failures. The decision circuitry may designate the semiconductor device for an additional procedure, if the number of the identified failures is within a first number set. The decision circuitry may designate the semiconductor device for repair, if the number of the identified failures is within a second number set. The decision circuitry designate the semiconductor device for additional tests of the first type, if the number of the identified failures is within a third number set. The tests of a first type may be a hot sort procedure and the additional tests may be a cold final procedure.
摘要翻译：本发明涉及用于测试一个或多个半导体器件（例如封装芯片）的系统和方法。测试设备至少执行半导体器件上的第一类测试，并识别半导体器件中的故障（如果有的话）。确定了一些故障。在存在某些故障的情况下，决定电路确定重复测试或修复半导体器件是否更有效，如果它是可修复的。取决于所识别的故障的数量，半导体器件可以不同地分箱。如果所识别的故障的数量在第一数量集合内，则决定电路可以指定用于附加过程的半导体器件。如果所识别的故障的数量在第二数量集合内，则决定电路可以指定用于修复的半导体器件。如果所识别的故障的数量在第三数量集合内，则决定电路指定用于第一类型的附加测试的半导体器件。第一种类型的测试可能是热分类程序，附加测试可能是一个冷的最终程序。

6. 发明授权

US06321353B2 Intelligent binning for electrically repairable semiconductor chips 失效
标题翻译：用于电可修复半导体芯片的智能合并
公开(公告)号：US06321353B2
公开(公告)日：2001-11-20
申请号：US09758868
申请日：2001-01-10
申请人： Brett M. Debenham
发明人： Brett M. Debenham
IPC分类号： H04B1700
CPC分类号： G01R31/01 , G01R31/2851 , G01R31/31718 , G01R31/319 , G11C29/44 , G11C29/56
摘要： The present invention relates to a system and method for testing one or more semiconductor devices (e.g., packaged chips). Test equipment performs at least tests of a first type on the semiconductor device and identifies failures in the semiconductor device, if any. A number of failures is determined. In the case where there are some failures, decision circuitry determines whether it is more efficient to repeat the tests or repair the semiconductor device, if it is repairable.
摘要翻译：本发明涉及用于测试一个或多个半导体器件（例如封装芯片）的系统和方法。测试设备至少执行半导体器件上的第一类测试，并识别半导体器件中的故障（如果有的话）。确定了一些故障。在存在某些故障的情况下，决定电路确定重复测试或修复半导体器件是否更有效，如果它是可修复的。

7. 发明授权

US5764650A Intelligent binning for electrically repairable semiconductor chips 失效
公开(公告)号：US5764650A
公开(公告)日：1998-06-09
申请号：US691335
申请日：1996-08-02
申请人： Brett M. Debenham
发明人： Brett M. Debenham
IPC分类号： G01R31/01 , G01R31/28 , G01R31/319 , G11C29/44 , G11C29/56 , G06F11/00
CPC分类号： G01R31/31718 , G01R31/01 , G01R31/319 , G11C29/44 , G01R31/2851 , G11C29/56
摘要： The present invention relates to a system and method for testing one or more semiconductor devices (e.g. packaged chips). Test equipment performs at least tests of a first type on the semiconductor device and identifies failures in the semiconductor device, if any. A number of failures is determined. In the case where there are some failures, decision circuitry determines whether it is more efficient to repeat the tests or repair the semiconductor device, if it is repairable. The semiconductor device may be binned differently depending on the number of identified failures. The decision circuitry may designate the semiconductor device for an additional procedure, if the number of the identified failures is within a first number set. The decision circuitry may designate the semiconductor device for repair, if the number of the identified failures is within a second number set. The decision circuitry designate the semiconductor device for additional tests of the first type, if the number of the identified failures is within a third number set. The tests of a first type may be a hot sort procedure and the additional tests may be a cold final procedure.

8. 发明授权

US6138256A Intelligent binning for electrically repairable semiconductor chips 失效
标题翻译：用于电可修复半导体芯片的智能合并
公开(公告)号：US6138256A
公开(公告)日：2000-10-24
申请号：US49457
申请日：1998-03-27
申请人： Brett M. Debenham
发明人： Brett M. Debenham
IPC分类号： G01R31/01 , G01R31/28 , G01R31/319 , G11C29/44 , G11C29/56 , G11C29/00
CPC分类号： G01R31/01 , G01R31/31718 , G01R31/319 , G11C29/44 , G11C29/56 , G01R31/2851
摘要： The present invention relates to a system and method for testing one or more semiconductor devices (e.g. packaged chips). Test equipment performs at least tests of a first type on the semiconductor device and identifies failures in the semiconductor device, if any. A number of failures is determined. In the case where there are some failures, decision circuitry determines whether it is more efficient to repeat the tests or repair the semiconductor device, if it is repairable. The semiconductor device may be binned differently depending on the number of identified failures. The decision circuitry may designate the semiconductor device for an additional procedure, if the number of the identified failures is within a first number set. The decision circuitry may designate the semiconductor device for repair, if the number of the identified failures is within a second number set. The decision circuitry designate the semiconductor device for additional tests of the first type, if the number of the identified failures is within a third number set. The tests of a first type may be a hot sort procedure and the additional tests may be a cold final procedure.
摘要翻译：本发明涉及用于测试一个或多个半导体器件（例如封装芯片）的系统和方法。测试设备至少执行半导体器件上的第一类测试，并识别半导体器件中的故障（如果有的话）。确定了一些故障。在存在某些故障的情况下，决定电路确定重复测试或修复半导体器件是否更有效，如果它是可修复的。取决于所识别的故障的数量，半导体器件可以不同地分箱。如果所识别的故障的数量在第一数量集合内，则决定电路可以指定用于附加过程的半导体器件。如果所识别的故障的数量在第二数量集合内，则决定电路可以指定用于修复的半导体器件。如果所识别的故障的数量在第三数量集合内，则决定电路指定用于第一类型的附加测试的半导体器件。第一种类型的测试可能是热分类程序，附加测试可能是一个冷的最终程序。

9. 发明授权

US06587980B2 Intelligent binning for electrically repairable semiconductor chips 失效
公开(公告)号：US06587980B2
公开(公告)日：2003-07-01
申请号：US10231728
申请日：2002-08-28
申请人： Brett M. Debenham
发明人： Brett M. Debenham
IPC分类号： H04B1200
CPC分类号： G01R31/01 , G01R31/2851 , G01R31/31718 , G01R31/319 , G11C29/44 , G11C29/56
摘要： The present invention relates to a system and method for testing one or more semiconductor devices (e.g., packaged chips). Test equipment performs at least tests of a first type on the semiconductor device and identifies failures in the semiconductor device, if any. A number of failures is determined. In the case where there are some failures, decision circuitry determines whether it is more efficient to repeat the tests or repair the semiconductor device, if it is repairable.

10. 发明授权

US06523144B2 Intelligent binning for electrically repairable semiconductor chips and method 失效
标题翻译：用于电可修复半导体芯片的智能合并和方法
公开(公告)号：US06523144B2
公开(公告)日：2003-02-18
申请号：US09943777
申请日：2001-08-30
申请人： Brett M. Debenham
发明人： Brett M. Debenham
IPC分类号： H04B1700
CPC分类号： G01R31/01 , G01R31/2851 , G01R31/31718 , G01R31/319 , G11C29/44 , G11C29/56
摘要： The present invention relates to a system and method for testing one or more semiconductor devices (e.g., packaged chips). Test equipment performs at least tests of a first type on the semiconductor device and identifies failures in the semiconductor device, if any. A number of failures is determined. In the case where there are some failures, decision circuitry determines whether it is more efficient to repeat the tests or repair the semiconductor device, if it is repairable.
摘要翻译：本发明涉及用于测试一个或多个半导体器件（例如封装芯片）的系统和方法。测试设备至少执行半导体器件上的第一类测试，并识别半导体器件中的故障（如果有的话）。确定了一些故障。在存在某些故障的情况下，决定电路确定重复测试或修复半导体器件是否更有效，如果它是可修复的。

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