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1. 发明授权

US06809505B2 Storage system and method of detecting an improper cable connection in the storage system 有权
标题翻译：存储系统和检测存储系统中不正确的电缆连接的方法
公开(公告)号：US06809505B2
公开(公告)日：2004-10-26
申请号：US10255223
申请日：2002-09-26
申请人： Douglas E. Peeke , Brian K. Bailey , Geoffrey Reid , James M. Tuttle
发明人： Douglas E. Peeke , Brian K. Bailey , Geoffrey Reid , James M. Tuttle
IPC分类号： G01R1900
CPC分类号： G06F13/409 , G06F3/0601 , G06F11/006 , G06F2003/0697
摘要： Described are a system and method of detecting an improperly connected cable in a storage system. A system includes an enclosure having boards. Each board of the enclosure has a communications port that receives a message identifying a redundant backend network to which that board is connected. The enclosure determines whether the system has an improper cable connection by determining from the messages whether the boards are connected to the same redundant backend network.
摘要翻译：描述了在存储系统中检测不正确连接的电缆的系统和方法。系统包括具有板的外壳。机箱的每个板都有一个通信端口，该通信端口接收标识该板连接到的冗余后端网络的消息。外壳通过从消息中确定电路板是否连接到相同的冗余后端网络来确定系统是否具有不正确的电缆连接。

2. 发明授权

US07194673B2 Detecting intermittent losses of synchronization in a fibre channel loop 有权
标题翻译：检测光纤通道环路间的同步丢失
公开(公告)号：US07194673B2
公开(公告)日：2007-03-20
申请号：US10327338
申请日：2002-12-20
申请人： James M. Tuttle , Douglas E. Peeke , Geoffrey Reid
发明人： James M. Tuttle , Douglas E. Peeke , Geoffrey Reid
IPC分类号： H03M13/33 , H03M13/01
CPC分类号： H04L1/22
摘要： Described are a storage system and method for detecting an intermittent loss of synchronization in communication signals received by an enclosure connected to a Fibre Channel loop. A control board produces a first signal representing a status of communication signals received by the control board. The first signal is in one of a plurality of logical states. A first logical state indicates that the status of the communication signals is invalid and a second logical state indicates that the status of the communication signals is valid. The control board includes a glitch-detection circuit that places a second signal in an asserted logical state when the first signal is in the first logical state during a time interval and holds the second signal at the asserted logical state when the first signal transitions from being in the first logical state to being in the second logical state during the time interval.
摘要翻译：描述了一种用于检测由连接到光纤通道环路的外壳接收的通信信号中的间歇性同步丢失的存储系统和方法。控制板产生表示由控制板接收的通信信号的状态的第一信号。第一信号是多个逻辑状态之一。第一逻辑状态表示通信信号的状态无效，第二逻辑状态表示通信信号的状态有效。控制板包括毛刺检测电路，当第一信号在时间间隔期间处于第一逻辑状态时，将第二信号置于有效逻辑状态，并且当第一信号从第处于处于第二逻辑状态的第一逻辑状态。

3. 发明授权

US07120721B1 Fibre channel architecture port having optical and copper connectors 有权
标题翻译：具有光纤和铜连接器的光纤通道架构端口
公开(公告)号：US07120721B1
公开(公告)日：2006-10-10
申请号：US10228513
申请日：2002-08-27
申请人： James M. Tuttle , Douglas E. Peeke
发明人： James M. Tuttle , Douglas E. Peeke
IPC分类号： G06F9/00 , G06F13/38 , G02B6/36
CPC分类号： G06F13/385
摘要： First and second inputs are associated with a port. Logic produces indications to software to cause the first input and second input to appear as a single input to the software. The logic produces an indication that no signal is present on either the first input or the second input. When a port bypass controller is coupled to the port, the logic produces an indication that both the first and second inputs are bypassed. When the port bypass controller is coupled to a Fibre Channel arbitrated loop, the logic produces a first signal to control whether the first input is included on the Fibre Channel arbitrated loop or bypassed, and a second signal to control whether the second input is included in the Fibre Channel arbitrated loop or bypassed.
摘要翻译：第一个和第二个输入与端口相关联。逻辑产生软件的指示，使第一个输入和第二个输入显示为软件的单个输入。逻辑产生在第一输入或第二输入上不存在信号的指示。当端口旁路控制器耦合到端口时，逻辑产生第一和第二输入被旁路的指示。当端口旁路控制器耦合到光纤通道仲裁环路时，逻辑产生第一信号以控制第一输入是包括在光纤通道仲裁环路还是被旁路，以及第二信号以控制第二输入是否包括在光纤通道仲裁环路或旁路。

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