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1. 发明授权

US07310036B2 Heat sink for integrated circuit devices 有权
标题翻译：集成电路器件的散热片
公开(公告)号：US07310036B2
公开(公告)日：2007-12-18
申请号：US10905546
申请日：2005-01-10
申请人： Douglas D. Coolbaugh , Ebenezer E. Eshun , Terence B. Hook , Robert M. Rassel , Edmund J. Sprogis , Anthony K Stamper , William J. Murphy
发明人： Douglas D. Coolbaugh , Ebenezer E. Eshun , Terence B. Hook , Robert M. Rassel , Edmund J. Sprogis , Anthony K Stamper , William J. Murphy
IPC分类号： H01C1/08
CPC分类号： H01C7/1013 , H01C1/084 , H01L2924/0002 , Y10T29/49083 , Y10T29/49085 , Y10T29/49099 , Y10T29/49144 , Y10T29/49147 , H01L2924/00
摘要： A resistor with heat sink is provided. The heat sink includes a conductive path having metal or other thermal conductor having a high thermal conductivity. To avoid shorting the electrical resistor to ground with the thermal conductor, a thin layer of high thermal conductivity electrical insulator is interposed between the thermal conductor and the body of the resistor. Accordingly, a resistor can carry large amounts of current because the high conductivity thermal conductor will conduct heat away from the resistor to a heat sink. Various configurations of thermal conductors and heat sinks are provided offering good thermal conductive properties in addition to reduced parasitic capacitances and other parasitic electrical effects, which would reduce the high frequency response of the electrical resistor.
摘要翻译：提供带散热片的电阻。散热器包括具有导热性高的金属或其它热导体的导电路径。为了避免使用热导体将电阻器短路接地，在热导体和电阻体之间插入有一层薄导电电绝缘体。因此，电阻器可承载大量的电流，因为高导电性热导体将热量从电阻器传导到散热器。除了降低寄生电容和其他寄生电效应之外，提供各种配置的导热体和散热片，提供良好的导热性能，这将降低电阻器的高频响应。

2. 发明授权

US08881379B2 Method of making heat sink for integrated circuit devices 有权
标题翻译：为集成电路器件制造散热片的方法
公开(公告)号：US08881379B2
公开(公告)日：2014-11-11
申请号：US13460871
申请日：2012-05-01
申请人： Douglas D. Coolbaugh , Ebenezer E. Eshun , Terence B. Hook , Robert M. Rassel , Edmund J. Sprogis , Anthony K. Stamper , William J. Murphy
发明人： Douglas D. Coolbaugh , Ebenezer E. Eshun , Terence B. Hook , Robert M. Rassel , Edmund J. Sprogis , Anthony K. Stamper , William J. Murphy
IPC分类号： H05B3/00 , H01C1/084 , H01C7/10
CPC分类号： H01C7/1013 , H01C1/084 , H01L2924/0002 , Y10T29/49083 , Y10T29/49085 , Y10T29/49099 , Y10T29/49144 , Y10T29/49147 , H01L2924/00
摘要： A resistor with heat sink is provided. The heat sink includes a conductive path having metal or other thermal conductor having a high thermal conductivity. To avoid shorting the electrical resistor to ground with the thermal conductor, a thin layer of high thermal conductivity electrical insulator is interposed between the thermal conductor and the body of the resistor. Accordingly, a resistor can carry large amounts of current because the high conductivity thermal conductor will conduct heat away from the resistor to a heat sink. Various configurations of thermal conductors and heat sinks are provided offering good thermal conductive properties in addition to reduced parasitic capacitances and other parasitic electrical effects, which would reduce the high frequency response of the electrical resistor.
摘要翻译：提供带散热片的电阻。散热器包括具有导热性高的金属或其它热导体的导电路径。为了避免使用热导体将电阻器短路接地，在热导体和电阻体之间插入有一层薄导电电绝缘体。因此，电阻器可承载大量的电流，因为高导电性热导体将热量从电阻器传导到散热器。除了降低寄生电容和其他寄生电效应之外，提供各种配置的导热体和散热片，提供良好的导热性能，这将降低电阻器的高频响应。

3. 发明授权

US07994895B2 Heat sink for integrated circuit devices 失效
标题翻译：散热器用于集成电路设备
公开(公告)号：US07994895B2
公开(公告)日：2011-08-09
申请号：US11777389
申请日：2007-07-13
申请人： Douglas D. Coolbaugh , Ebenezer E. Eshun , Terence B. Hook , Robert M. Rassel , Edmund J. Sprogis , Anthony K. Stamper , William J. Murphy
发明人： Douglas D. Coolbaugh , Ebenezer E. Eshun , Terence B. Hook , Robert M. Rassel , Edmund J. Sprogis , Anthony K. Stamper , William J. Murphy
IPC分类号： H01C1/08
CPC分类号： H01C7/1013 , H01C1/084 , H01L2924/0002 , Y10T29/49083 , Y10T29/49085 , Y10T29/49099 , Y10T29/49144 , Y10T29/49147 , H01L2924/00
摘要： A resistor with heat sink is provided. The heat sink includes a conductive path having metal or other thermal conductor having a high thermal conductivity. To avoid shorting the electrical resistor to ground with the thermal conductor, a thin layer of high thermal conductivity electrical insulator is interposed between the thermal conductor and the body of the resistor. Accordingly, a resistor can carry large amounts of current because the high conductivity thermal conductor will conduct heat away from the resistor to a heat sink. Various configurations of thermal conductors and heat sinks are provided offering good thermal conductive properties in addition to reduced parasitic capacitances and other parasitic electrical effects, which would reduce the high frequency response of the electrical resistor.
摘要翻译：提供带散热片的电阻。散热器包括具有导热性高的金属或其它热导体的导电路径。为了避免使用热导体将电阻器短路接地，在热导体和电阻体之间插入有一层薄导电电绝缘体。因此，电阻器可承载大量的电流，因为高导电性热导体将热量从电阻器传导到散热器。除了降低寄生电容和其他寄生电效应之外，提供各种配置的导热体和散热片，提供良好的导热性能，这将降低电阻器的高频响应。

4. 发明授权

US07494912B2 Terminal pad structures and methods of fabricating same 有权
标题翻译：端子焊盘结构及其制造方法
公开(公告)号：US07494912B2
公开(公告)日：2009-02-24
申请号：US11953927
申请日：2007-12-11
申请人： Douglas D. Coolbaugh , Daniel C. Edelstein , Ebenezer E. Eshun , Zhong-Xiang He , Robert M. Rassel , Anthony K. Stamper
发明人： Douglas D. Coolbaugh , Daniel C. Edelstein , Ebenezer E. Eshun , Zhong-Xiang He , Robert M. Rassel , Anthony K. Stamper
IPC分类号： H01L21/44
CPC分类号： H01L24/11 , H01L23/3192 , H01L24/03 , H01L24/05 , H01L24/13 , H01L2224/02166 , H01L2224/0401 , H01L2224/05006 , H01L2224/05007 , H01L2224/05022 , H01L2224/05554 , H01L2224/05568 , H01L2224/05572 , H01L2224/13007 , H01L2224/13022 , H01L2224/13023 , H01L2224/13099 , H01L2224/131 , H01L2224/13111 , H01L2224/16 , H01L2224/45124 , H01L2924/0001 , H01L2924/00014 , H01L2924/0002 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/01073 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/13091 , H01L2924/14 , H01L2924/00 , H01L2224/48 , H01L2224/05552
摘要： Terminal pads and methods of fabricating terminal pads. The methods including forming a conductive diffusion barrier under a conductive pad in or overlapped by a passivation layer comprised of multiple dielectric layers including diffusion barrier layers. The methods including forming the terminal pads subtractively or by a damascene process.
摘要翻译：端子焊盘和制造端子焊盘的方法。所述方法包括在由包括扩散阻挡层的多个电介质层组成的钝化层的内部或与其重叠的导电焊盘下方形成导电扩散阻挡层。所述方法包括减法地形成端子焊盘或通过镶嵌工艺。

5. 发明授权

US08435864B2 Process for single and multiple level metal-insulator-metal integration with a single mask 有权
标题翻译：单层和多层金属绝缘体金属与单一掩模集成的工艺
公开(公告)号：US08435864B2
公开(公告)日：2013-05-07
申请号：US13432440
申请日：2012-03-28
申请人： Anil K. Chinthakindi , Douglas D. Coolbaugh , Keith E. Downes , Ebenezer E. Eshun , Zhong-Xiang He , Robert M. Rassel , Anthony K. Stamper
发明人： Anil K. Chinthakindi , Douglas D. Coolbaugh , Keith E. Downes , Ebenezer E. Eshun , Zhong-Xiang He , Robert M. Rassel , Anthony K. Stamper
IPC分类号： H01L21/28
CPC分类号： H01L21/32139 , H01L21/32136 , H01L28/75
摘要： A method of fabricating a MIM capacitor is provided. The method includes providing a substrate including a dielectric layer formed on a first conductive layer and a second conductive layer formed over the dielectric layer, and patterning a mask on the second conductive layer. Exposed portions of the second conductive layer are removed to form an upper plate of a MIM capacitor having edges substantially aligned with respective edges of the mask. The upper plate is undercut so that edges of the upper plate are located under the mask. Exposed portions of the dielectric layer and the first conductive layer are removed using the mask to form a capacitor dielectric layer and a lower plate of the MIM capacitor having edges substantially aligned with respective edges of the mask.
摘要翻译：提供一种制造MIM电容器的方法。该方法包括提供包括形成在第一导电层上的电介质层和形成在电介质层上的第二导电层的衬底，以及在第二导电层上构图掩模。去除第二导电层的暴露部分以形成具有与掩模的相应边缘基本对齐的边缘的MIM电容器的上板。上板被切下，使得上板的边缘位于掩模下方。使用掩模去除电介质层和第一导电层的暴露部分，以形成MIM电容器的电容器电介质层和具有基本上与掩模的各个边缘对准的边缘的MIM电容器的下板。

6. 发明授权

US07239006B2 Resistor tuning 有权
标题翻译：电阻调谐
公开(公告)号：US07239006B2
公开(公告)日：2007-07-03
申请号：US10709115
申请日：2004-04-14
申请人： Douglas D. Coolbaugh , Ebenezer E. Eshun , Robert M. Rassel , Anthony K. Stamper
发明人： Douglas D. Coolbaugh , Ebenezer E. Eshun , Robert M. Rassel , Anthony K. Stamper
IPC分类号： H01L29/00
CPC分类号： H01C17/267
摘要： A structure for resistors and the method for tuning the same. The resistor comprises an electrically conducting region coupled to a liner region. Both the electrically conducting region and the liner region are electrically coupled to first and second contact regions. A voltage difference is applied between the first and second contact regions. As a result, a current flows between the first and second contact regions in the electrically conducting region. The voltage difference and the materials of the electrically conducting region and the liner region are such that electromigration occurs only in the electrically conducting region. As a result, a void region within the electrically conducting region expands in the direction of the flow of the charged particles constituting the current. Because the resistor loses a conducting portion of the electrically conducting region to the void region, the resistance of the resistor is increased (i.e., tuned).
摘要翻译：电阻器结构及其调谐方法。电阻器包括耦合到衬垫区域的导电区域。导电区域和衬里区域都电耦合到第一和第二接触区域。在第一和第二接触区域之间施加电压差。结果，电流在导电区域中的第一和第二接触区域之间流动。导电区域和衬垫区域的电压差和材料使得电迁移仅在导电区域中发生。结果，导电区域内的空隙区域在构成电流的带电粒子的流动方向上膨胀。因为电阻器将导电区域的导电部分损失到空隙区域，电阻器的电阻增加（即调谐）。

7. 发明申请

US20110108919A1 METHOD OF FABRICATING A PRECISION BURIED RESISTOR 审中-公开
标题翻译：制造精密电阻器的方法
公开(公告)号：US20110108919A1
公开(公告)日：2011-05-12
申请号：US13006001
申请日：2011-01-13
申请人： Anil K. Chinthakindi , Douglas D. Coolbaugh , Keith E. Downes , Ebenezer E. Eshun , John E. Florkey , Heidi L. Greer , Robert M. Rassel , Anthony K. Stamper , Kunal Vaed
发明人： Anil K. Chinthakindi , Douglas D. Coolbaugh , Keith E. Downes , Ebenezer E. Eshun , John E. Florkey , Heidi L. Greer , Robert M. Rassel , Anthony K. Stamper , Kunal Vaed
IPC分类号： H01L27/12
CPC分类号： H01L29/8605 , H01L27/0802 , H01L28/20
摘要： The present invention provides a semiconductor structure including a buried resistor with improved control, in which the resistor is fabricated in a region of a semiconductor substrate beneath a well region that is also present in the substrate. In accordance with the present invention, the inventive structure includes a semiconductor substrate containing at least a well region; and a buried resistor located in a region of the semiconductor substrate that is beneath said well region. The present invention also provides a method of fabricating such a structure in which a deep ion implantation process is used to form the buried resistor and a shallower ion implantation process is used in forming the well region.
摘要翻译：本发明提供一种包括具有改进控制的掩埋电阻器的半导体结构，其中电阻器制造在半导体衬底的也存在于衬底中的阱区域下方的区域中。根据本发明，本发明的结构包括至少含有一个阱区的半导体衬底; 以及位于半导体衬底的位于所述阱区之下的区域中的掩埋电阻器。本发明还提供一种制造这样的结构的方法，其中使用深离子注入工艺来形成掩埋电阻器，并且在形成阱区域中使用较浅的离子注入工艺。

8. 发明授权

US07829452B2 Terminal pad structures and methods of fabricating same 有权
标题翻译：端子焊盘结构及其制造方法
公开(公告)号：US07829452B2
公开(公告)日：2010-11-09
申请号：US12348934
申请日：2009-01-06
申请人： Douglas D. Coolbaugh , Daniel C. Edelstein , Ebenezer E. Eshun , Zhong-Xiang He , Robert M. Rassel , Anthony K. Stamper
发明人： Douglas D. Coolbaugh , Daniel C. Edelstein , Ebenezer E. Eshun , Zhong-Xiang He , Robert M. Rassel , Anthony K. Stamper
IPC分类号： H01L21/44
CPC分类号： H01L24/11 , H01L23/3192 , H01L24/03 , H01L24/05 , H01L24/13 , H01L2224/02166 , H01L2224/0401 , H01L2224/05006 , H01L2224/05007 , H01L2224/05022 , H01L2224/05554 , H01L2224/05568 , H01L2224/05572 , H01L2224/13007 , H01L2224/13022 , H01L2224/13023 , H01L2224/13099 , H01L2224/131 , H01L2224/13111 , H01L2224/16 , H01L2224/45124 , H01L2924/0001 , H01L2924/00014 , H01L2924/0002 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/01073 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/13091 , H01L2924/14 , H01L2924/00 , H01L2224/48 , H01L2224/05552
摘要： Terminal pads and methods of fabricating terminal pads. The methods including forming a conductive diffusion barrier under a conductive pad in or overlapped by a passivation layer comprised of multiple dielectric layers including diffusion barrier layers. The methods including forming the terminal pads subtractively or by a damascene process.
摘要翻译：端子焊盘和制造端子焊盘的方法。所述方法包括在由包括扩散阻挡层的多个电介质层组成的钝化层的内部或与其重叠的导电焊盘下方形成导电扩散阻挡层。所述方法包括减法地形成端子焊盘或通过镶嵌工艺。

9. 发明申请

US20090155993A1 TERMINAL PAD STRUCTURES AND METHODS OF FABRICATING SAME 有权
标题翻译：端子板结构及其制造方法
公开(公告)号：US20090155993A1
公开(公告)日：2009-06-18
申请号：US12348934
申请日：2009-01-06
申请人： Douglas D. Coolbaugh , Daniel C. Edelstein , Ebenezer E. Eshun , Zhong-Xiang He , Robert M. Rassel , Anthony K. Stamper
发明人： Douglas D. Coolbaugh , Daniel C. Edelstein , Ebenezer E. Eshun , Zhong-Xiang He , Robert M. Rassel , Anthony K. Stamper
IPC分类号： H01L21/60
CPC分类号： H01L24/11 , H01L23/3192 , H01L24/03 , H01L24/05 , H01L24/13 , H01L2224/02166 , H01L2224/0401 , H01L2224/05006 , H01L2224/05007 , H01L2224/05022 , H01L2224/05554 , H01L2224/05568 , H01L2224/05572 , H01L2224/13007 , H01L2224/13022 , H01L2224/13023 , H01L2224/13099 , H01L2224/131 , H01L2224/13111 , H01L2224/16 , H01L2224/45124 , H01L2924/0001 , H01L2924/00014 , H01L2924/0002 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/01073 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/13091 , H01L2924/14 , H01L2924/00 , H01L2224/48 , H01L2224/05552
摘要： Terminal pads and methods of fabricating terminal pads. The methods including forming a conductive diffusion barrier under a conductive pad in or overlapped by a passivation layer comprised of multiple dielectric layers including diffusion barrier layers. The methods including forming the terminal pads subtractively or by a damascene process.
摘要翻译：端子焊盘和制造端子焊盘的方法。所述方法包括在由包括扩散阻挡层的多个电介质层组成的钝化层的内部或与其重叠的导电焊盘下方形成导电扩散阻挡层。所述方法包括减法地形成端子焊盘或通过镶嵌工艺。

10. 发明授权

US07361993B2 Terminal pad structures and methods of fabricating same 有权
标题翻译：端子焊盘结构及其制造方法
公开(公告)号：US07361993B2
公开(公告)日：2008-04-22
申请号：US10908346
申请日：2005-05-09
申请人： Douglas D. Coolbaugh , Daniel C. Edelstein , Ebenezer E. Eshun , Zhong-Xiang He , Robert M. Rassel , Anthony K. Stamper
发明人： Douglas D. Coolbaugh , Daniel C. Edelstein , Ebenezer E. Eshun , Zhong-Xiang He , Robert M. Rassel , Anthony K. Stamper
IPC分类号： H01L29/40
CPC分类号： H01L24/11 , H01L23/3192 , H01L24/03 , H01L24/05 , H01L24/13 , H01L2224/02166 , H01L2224/0401 , H01L2224/05006 , H01L2224/05007 , H01L2224/05022 , H01L2224/05554 , H01L2224/05568 , H01L2224/05572 , H01L2224/13007 , H01L2224/13022 , H01L2224/13023 , H01L2224/13099 , H01L2224/131 , H01L2224/13111 , H01L2224/16 , H01L2224/45124 , H01L2924/0001 , H01L2924/00014 , H01L2924/0002 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/01073 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/13091 , H01L2924/14 , H01L2924/00 , H01L2224/48 , H01L2224/05552
摘要： Terminal pads and methods of fabricating terminal pads. The methods including forming a conductive diffusion barrier under a conductive pad in or overlapped by a passivation layer comprised of multiple dielectric layers including diffusion barrier layers. The methods including forming the terminal pads subtractively or by a damascene process.
摘要翻译：端子焊盘和制造端子焊盘的方法。所述方法包括在由包括扩散阻挡层的多个电介质层组成的钝化层的内部或与其重叠的导电焊盘下方形成导电扩散阻挡层。所述方法包括减法地形成端子焊盘或通过镶嵌工艺。

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