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1. 发明授权

US5440245A Logic module with configurable combinational and sequential blocks 失效
标题翻译：具有可组态组合和顺序块的逻辑模块
公开(公告)号：US5440245A
公开(公告)日：1995-08-08
申请号：US028789
申请日：1993-03-09
申请人： Douglas C. Galbraith , Abbas El Gamal , Jonathan W. Greene
发明人： Douglas C. Galbraith , Abbas El Gamal , Jonathan W. Greene
IPC分类号： H03K3/037 , H03K19/173 , H03K19/177
CPC分类号： H03K19/1737 , H03K3/037
摘要： A logic module includes a first and a second two-input multiplexer each having first and second data inputs. Both the first and second multiplexer include a select input, both of which are connected to the output of a two-input logic gate of a first type having first and second data inputs. The inputs to the first and second two-input multiplexers are sourced with data signals from a first group. One input of each of the logic gates is sourced from a data signal of a second group and the other input of each of the logic gates is sourced from a data signal of a third group. A third two-input multiplexer has its first and second data inputs connected the outputs of the first and second multiplexers, respectively. A select input of the third two-input multiplexer is connected to the output of a two input logic gate of a second type having first and second data inputs. The output of the third two-input multiplexer is connected to a first data input of a fourth two-input multiplexer having a HOLD1 input coupled to its select input. Its output is and a CLEAR input are presented to an AND gate whose output is connected to the second data input of the fourth two-input multiplexer and to the first data input of a fifth two-input multiplexer. The select input of the fifth two-input multiplexer is connected to a HOLD2 input. Its output and the CLEAR input are presented to an AND gate whose output is connected to the second data input of the fifth two-input multiplexer and to an output node. The CLEAR, HOLD1 and HOLD2 inputs are defined by combinations of signals from a data signal of a third group which may contain a data signal of one of the other groups.
摘要翻译：逻辑模块包括第一和第二双输入多路复用器，每个具有第一和第二数据输入。第一和第二多路复用器都包括选择输入，它们都连接到具有第一和第二数据输入的具有第一类型的双输入逻辑门的输出。对第一和第二双输入多路复用器的输入来自第一组的数据信号。每个逻辑门的一个输入源自第二组的数据信号，并且每个逻辑门的另一个输入源自第三组的数据信号。第三双输入多路复用器具有分别连接第一和第二多路复用器的输出的第一和第二数据输入。第三双输入多路复用器的选择输入连接到具有第一和第二数据输入的具有第二类型的两输入逻辑门的输出。第三双输入多路复用器的输出连接到具有耦合到其选择输入的HOLD1输入的第四双输入多路复用器的第一数据输入。其输出为CLEAR输入，并将其输出连接到第四个双输入多路复用器的第二数据输入端和第五个双输入多路复用器的第一个数据输入端的与门。第五个双输入多路复用器的选择输入连接到一个HOLD2输入。其输出和CLEAR输入被呈现给AND门，其输出端连接到第五个双输入多路复用器的第二个数据输入端和一个输出节点。 CLEAR，HOLD1和HOLD2输入由来自第三组的数据信号的组合组成，其可以包含其他组中的一个的数据信号。

2. 发明授权

US5371414A Simultaneous multiple antifuse programming method 失效
标题翻译：同时多重反熔丝编程方法
公开(公告)号：US5371414A
公开(公告)日：1994-12-06
申请号：US67381
申请日：1993-05-26
申请人： Douglas C. Galbraith
发明人： Douglas C. Galbraith
IPC分类号： G11C17/14 , G11C17/18 , H01L21/82 , H01L23/525 , H03K19/177 , H01H37/76
CPC分类号： H01L23/5252 , G11C17/18 , H01L2924/0002
摘要： A method for simultaneously programming a plurality of antifuses each having a first electrode connected to a common node and each having a second electrode connected to an isolated node electrically isolated from the nodes of each of the other antifuses includes the steps of precharging the common node and the isolated nodes to an intermediate voltage potential selected to minimize the stress on all antifuses; precharging the isolated nodes of selected ones of the antifuses to a first programming voltage potential placing a second programming voltage potential on said common node, the first and second programming voltage potentials selected such that the difference between them is sufficient to cause programming of said antifuses and such that said intermediate potential is substantially centered between them, waiting a predetermined amount of time; and measuring the current flowing between the common node isolated nodes. If the measured current indicates that the desired antifuse has not been programmed the programming process may be attempted a preselected number of times. After the selected antifuses have been programmed, they are individually soaked by passing a soaking current through them.
摘要翻译：一种用于同时编程多个反熔丝的方法，每个反熔丝具有连接到公共节点的第一电极，并且每个具有连接到与每个其它反熔丝的每个的电气隔离的隔离节点的第二电极包括以下步骤：对所述公共节点进行预充电，所述隔离节点被选择为使所有反熔丝处的应力最小化的中间电压电位; 将所选择的反熔丝的隔离节点预充电到在所述公共节点上施加第二编程电压电位的第一编程电压电位，所选择的第一和第二编程电压电位使得它们之间的差异足以导致所述反熔丝的编程，使得所述中间电位基本上位于它们之间，等待预定量的时间; 并测量在公共节点隔离节点之间流动的电流。如果测量的电流指示所需的反熔丝未被编程，则可以预先编程编程过程。在所选择的反熔丝被编程之后，通过使浸泡电流通过它们而单独浸泡。

3. 发明授权

US4945267A Integrated circuit bus switching circuit 失效
标题翻译：集成电路总线切换电路
公开(公告)号：US4945267A
公开(公告)日：1990-07-31
申请号：US295402
申请日：1989-01-10
申请人： Douglas C. Galbraith
发明人： Douglas C. Galbraith
IPC分类号： H03K17/16 , H03K17/30 , H03K17/693 , H03K19/173
CPC分类号： H03K17/302 , H03K17/161 , H03K17/693 , H03K19/1732
摘要： A circuit is provided for switching an internal bus of an integrated circuit between an input/output pad on the integrated circuit and a circuit node of the integrated circuit. A first switch is connected between the input/output pad and the internal bus. A second switch is connected between the circuit node and the internal bus. A high voltage detector senses the presence or absence of a voltage exceeding a preselected threshold on the input-output pad. The high voltage detector assumes a first state if the voltage on the input/output pad exceeds the preselected threshold, and assumes a second state if the voltage on the input/output pad does not exceed the preselected threshold. Switch control circuitry responsive to the high voltage detector activates either the first or second switch depending upon the output of the high voltage detector. Circuitry is provided to prevent the first and second switches from being active simultaneously and for lowering the capacitance of the input/output pad.
摘要翻译：提供一种用于在集成电路上的输入/输出焊盘和集成电路的电路节点之间切换集成电路的内部总线的电路。第一个开关连接在输入/输出板和内部总线之间。第二个开关连接在电路节点和内部总线之间。高电压检测器检测输入输出焊盘上是否存在超过预选阈值的电压。如果输入/输出焊盘上的电压超过预选阈值，则高电压检测器将呈现第一状态，如果输入/输出焊盘上的电压不超过预选阈值，则该电压将呈现第二状态。响应于高电压检测器的开关控制电路根据高压检测器的输出激活第一或第二开关。提供电路以防止第一和第二开关同时被激活并且用于降低输入/输出焊盘的电容。

4. 发明授权

US5286992A Low voltage device in a high voltage substrate 失效
标题翻译：高电压基板中的低电压器件
公开(公告)号：US5286992A
公开(公告)日：1994-02-15
申请号：US38550
申请日：1993-03-29
申请人： Michael G. Ahrens , Douglas C. Galbraith , Abdelshafy Eltoukhy
发明人： Michael G. Ahrens , Douglas C. Galbraith , Abdelshafy Eltoukhy
IPC分类号： H01L27/02 , H01L27/088 , H01L29/68 , H01L29/78
CPC分类号： H01L27/0218 , H01L27/088 , Y10S257/901
摘要： A semiconductor or substrate of a first conductivity type includes a well structure of a second conductivity type formed therein. A first low voltage MOS transistor includes spaced apart source and drain regions of the first conductivity type in the well. A first transistor gate lies above a channel region which is disposed between the source and drain regions of the first low voltage MOS transistor and is separated therefrom by a gate dielectric having a first thickness. A second high voltage transistor includes spaced apart source and drain regions of the first conductivity type in the well. A second transistor gate lies above a channel region which is disposed between the source and drain regions of the second high voltage transistor and is separated therefrom by a gate dielectric having a second thickness which is greater than the thickness of the gate dielectric of the first low voltage MOS transistor. A first contact diffusion, having the same conductivity type as the well, is located at the edge of the well closest to the first low voltage transistor, and is connected to a source of voltage. A second contact diffusion, having the same conductivity type as the well, is located at the edge of the well closest to the second high voltage transistor, and is also connected to the source of voltage.
摘要翻译：第一导电类型的半导体或衬底包括形成在其中的第二导电类型的阱结构。第一低电压MOS晶体管在阱中包括第一导电类型的间隔开的源极和漏极区。第一晶体管栅极位于沟道区之上，沟道区设置在第一低电压MOS晶体管的源极和漏极区之间，并且通过具有第一厚度的栅极电介质与沟道区分离。第二高压晶体管包括在井中具有第一导电类型的间隔开的源极和漏极区域。第二晶体管栅极位于沟道区之上，沟道区设置在第二高电压晶体管的源极和漏极区之间，并且通过具有大于第一低的栅极电介质的厚度的第二厚度的栅极电介质与沟道区分离电压MOS晶体管。具有与阱相同的导电类型的第一接触扩散部位于最靠近第一低压晶体管的阱的边缘处，并连接到电压源。具有与阱相同的导电类型的第二接触扩散部位于最靠近第二高压晶体管的阱的边缘处，并且还连接到电压源。

5. 发明授权

US5130777A Apparatus for improving antifuse programming yield and reducing antifuse programming time 失效
标题翻译：改进抗体编程和减少抗体编程时间的设备
公开(公告)号：US5130777A
公开(公告)日：1992-07-14
申请号：US638517
申请日：1991-01-04
申请人： Douglas C. Galbraith , Steve S. Chiang , Abdelshafy A. Eltoukhy , Esmat Z. Hamdy
发明人： Douglas C. Galbraith , Steve S. Chiang , Abdelshafy A. Eltoukhy , Esmat Z. Hamdy
IPC分类号： G11C17/14 , G11C17/16 , H01L21/82 , H01L23/525
CPC分类号： G11C17/16 , H01L23/5252 , H01L2924/0002 , H01L2924/3011
摘要： The present invention includes four approaches to reduce the unintended programming of antifuses while programming selected antifuses and to decrease the programming time. The first approach includes circuitry to maintain the voltage placed on unselected antifuses at a constant level by use of a voltage source. According to the second approach, a resistor is included in series with the voltage source. According to the third approach, a diode is included in series with the voltage source. According to the fourth approach, a MOS implementation of a diode is included in series with the voltage source.

6. 发明授权

US5017813A Input/output module with latches 失效
标题翻译：带锁存器的输入/输出模块
公开(公告)号：US5017813A
公开(公告)日：1991-05-21
申请号：US522389
申请日：1990-05-11
申请人： Douglas C. Galbraith , Jonathan W. Greene
发明人： Douglas C. Galbraith , Jonathan W. Greene
IPC分类号： G06F3/00 , H03K19/0175
CPC分类号： H03K19/017581 , H03K19/01759
摘要： An input/output module circuit for providing input/output interface functions in integrated circuits includes an input section and an output section electrically connected to an I/O pad of the integrated circuit. The input section includes an input buffer/level shifter for translating the logic signals from the outside world to CMOS compatible levels. The input buffer may be placed in a high impedance state by a control signal applied to a control input. The output of the input buffer/level shifter is connected to a first data input of a two-input multiplexer. The output of the two-input multiplexer is connected to an internal bus and to the second data input of the two-input multiplexer. The select input of the two-input multiplexer is connected to a control signal, preferably to the same control signal used to enable the input buffer/level shifter. The output section of the input/output module section of the present invention includes a two-input multiplexer having a first input connected to an internal data bus, and its output fed back to its second data input. Its select input is driven from a control signal. The output of the two-input multiplexer is also connected to the input of an HCT buffer. The output of the HCT buffer is connected to an I/O pad of the integrated circuit, which may be the same pad to which the input section is connected. The slew input of the HCT buffer is driven from a signal enabling slow or fast rise times. The enable input of the HCT buffer is driven from an enable signal which may be derived from other logic signals.

7. 发明授权

US5610534A Logic module for a programmable logic device 失效
标题翻译：可编程逻辑器件的逻辑模块
公开(公告)号：US5610534A
公开(公告)日：1997-03-11
申请号：US505830
申请日：1995-05-18
申请人： Douglas C. Galbraith , Abbas El Gamal , Jonathan W. Greene
发明人： Douglas C. Galbraith , Abbas El Gamal , Jonathan W. Greene
IPC分类号： H03K3/037 , H03K19/173 , H03K19/177
CPC分类号： H03K19/1737 , H03K3/037
摘要： A logic module includes first and second multiplexers each having two data inputs and a select input. Both select inputs are connected to the output of a two-input logic gate of a first type. The inputs to the first and second multiplexers comprise data signals from a first group. One input of each logic gate comprises a data signal of n second group and the other input of each logic gate comprises a data signal of a third group. A third multiplexer has first and second data inputs connected the outputs of the first and second multiplexers, respectively, and a select input connected to the output of a two-input logic gate of a second type. Its output is connected to a first data input of a fourth-multiplexer having a HOLD1 input coupled to its select input. Its output and a CLEAR input are presented to an AND gate whose output is connected to the second data input of the fourth multiplexer and to the first data input of a fifth multiplexer. The fifth multiplexer select input comprises a HOLD2 input. Its output and the CLEAR input ere presented to an AND gate whose output is connected to the second data input of the fifth multiplexer and to an output node. The CLEAR, HOLD1 and HOLD2 inputs comprise combinations of signals from a data signal of a third group which may contain data signals of one of the other groups.
摘要翻译：逻辑模块包括具有两个数据输入和选择输入的第一和第二多路复用器。两个选择输入都连接到第一类型的双输入逻辑门的输出。第一和第二多路复用器的输入包括来自第一组的数据信号。每个逻辑门的一个输入包括n个第二组的数据信号，并且每个逻辑门的另一个输入包括第三组的数据信号。第三复用器具有分别连接第一和第二多路复用器的输出的第一和第二数据输入以及连接到第二类型的双输入逻辑门的输出的选择输入。其输出连接到具有耦合到其选择输入的HOLD1输入的第四多路复用器的第一数据输入。其输出和CLEAR输入被呈现给AND门，其输出连接到第四多路复用器的第二数据输入端和第五多路复用器的第一数据输入端。第五多路复用器选择输入包括一个HOLD2输入。其输出和CLEAR输入被提供给AND门，其输出连接到第五多路复用器的第二数据输入端和输出节点。 CLEAR，HOLD1和HOLD2输入包括来自第三组的数据信号的信号的组合，其可以包含其他组之一的数据信号。

8. 发明授权

US5198705A Logic module with configurable combinational and sequential blocks 失效
标题翻译：具有可组态组合和顺序块的逻辑模块
公开(公告)号：US5198705A
公开(公告)日：1993-03-30
申请号：US773353
申请日：1991-10-07
申请人： Douglas C. Galbraith , Abbas El Gamal , Jonathan W. Greene
发明人： Douglas C. Galbraith , Abbas El Gamal , Jonathan W. Greene
IPC分类号： H03K3/037 , H03K19/173
CPC分类号： H03K19/1737 , H03K3/037
摘要： A logic module includes first and second multiplexers each having two data inputs and a select input. Both select inputs are connected to the output of a two-input logic gate of a first type. The inputs to the first and second multiplexers comprise data signals from a first group. One input of each logic gate comprises a data signal of a second group and the other input of each logic gate comprises a data signal of a third group. A third multiplexer has first and second data inputs connected the outputs of the first and second multiplexers, respectively, and a select input connected to the output of a two-input logic gate of a second type. Its output is connected to a first data input of a fourth multiplexer having a HOLD1 input coupled to its select input. Its output and a CLEAR input are presented to an AND gate whose output is connected to the second data input of the fourth multiplexer and to the first data input of a fifth multiplexer. The fifth multiplexer select input comprises a HOLD2 input. Its output and the CLEAR input are presented to an AND gate whose output is connected to the second data input of the fifth multiplexer and to an output node. The CLEAR, HOLD1 and HOLD2 inputs comprise combinations of signals from a data signal of a third group which may contain data signals of one of the other groups.
摘要翻译：逻辑模块包括具有两个数据输入和选择输入的第一和第二多路复用器。两个选择输入都连接到第一类型的双输入逻辑门的输出。第一和第二多路复用器的输入包括来自第一组的数据信号。每个逻辑门的一个输入包括第二组的数据信号，并且每个逻辑门的另一个输入包括第三组的数据信号。第三复用器具有分别连接第一和第二多路复用器的输出的第一和第二数据输入以及连接到第二类型的双输入逻辑门的输出的选择输入。其输出连接到具有耦合到其选择输入的HOLD1输入的第四多路复用器的第一数据输入。其输出和CLEAR输入被呈现给AND门，其输出连接到第四多路复用器的第二数据输入端和第五多路复用器的第一数据输入端。第五多路复用器选择输入包括一个HOLD2输入。其输出和CLEAR输入被提供给AND门，其输出连接到第五多路复用器的第二数据输入端和输出节点。 CLEAR，HOLD1和HOLD2输入包括来自第三组的数据信号的信号的组合，其可以包含其他组之一的数据信号。

9. 发明授权

US4871933A High-speed static differential sense amplifier 失效
标题翻译：高速静态差分放大器
公开(公告)号：US4871933A
公开(公告)日：1989-10-03
申请号：US239130
申请日：1988-08-31
申请人： Douglas C. Galbraith
发明人： Douglas C. Galbraith
IPC分类号： H03K3/356
CPC分类号： H03K3/356113
摘要： The high-speed static differential sense amplifier of the present invention is composed of two stages. The first stage uses a source follower to feed a set of dual complimentary current mirrors. The current mirrors in the source of the input devices convert the voltage difference supplied by the source follower into a current. This current is mirrored into the second stage by opposing pull-down and pull-up current mirrors from the first stage. The second stage current difference produces the large voltage swings needed to drive the digital logic.
摘要翻译：本发明的高速静态差动读出放大器由两个阶段组成。第一阶段使用源跟随器馈送一组双互补电流镜。输入设备的电源中的电流镜将源极跟随器提供的电压差转换为电流。该电流通过相反的第一级的下拉和上拉电流镜反射到第二级。第二级电流差产生驱动数字逻辑所需的大电压摆幅。

10. 发明授权

US4592359A Multi-channel implantable neural stimulator 失效
标题翻译：多通道植入式神经刺激器
公开(公告)号：US4592359A
公开(公告)日：1986-06-03
申请号：US719231
申请日：1985-04-02
申请人： Douglas C. Galbraith
发明人： Douglas C. Galbraith
IPC分类号： A61F11/00 , A61F11/04 , A61N1/36
CPC分类号： A61N1/36032
摘要： A combination of a transmitter and implantable receiver are disclosed wherein data is conveyed from transmitter to receiver utilizing a data format in which each channel to be stimulated is adapted to convey information in monopolar, bipolar or analog form.The data format includes two types of code words: transition words in which one bit is assigned to each channel and can be used to create monopolar pulsatile or bipolar pulsatile waveforms; and amplitude words which can create analog waveforms one channel at a time.An essential element of the output system is a current source digital to analog converter which responds to the code words to form the appropriate output on each channel. Each output is composed of a set of eight current sources, four with one polarity of current and the other four with the opposite polarity of current. In each group of four, the current sources are binarily related, I, 2I, 4I and 8I. In this arrangement each channel can supply 16 amplitudes times two polarities of current; meaning 32 current levels. This channel is simply a 5-bit digit to analog converter.The output circuitry contains charge balance switches. These switches are designed to recover residual charge when the current sources are off. They are also designed to current limit during charge recovery if the excess charge is too great so that they do not cause neural damage.Each channel charge balances (will not pass DC current or charge) and charge limits to prevent electrode damage and bone growth. The charge balancing is performed by the charge balancing switches and by the blocking capacitor. The charge limiting is performed by the blocking capacitor only.The charge level on each channel is defined using a switch network ladder which combines a plurality of parallel connected switches; closure of each switch doubles the current level handed off from the previous switch.
摘要翻译：公开了发射机和可植入接收机的组合，其中使用数据格式将数据从发射机传送到接收机，其中要刺激的每个信道适于以单极，双极或模拟形式传送信息。数据格式包括两种类型的代码字：其中一个位被分配给每个通道的转换字，并且可用于产生单极脉冲或双极脉冲波形; 和一次可以创建模拟波形一个通道的幅度字。输出系统的一个基本要素是电流源数模转换器，其响应于代码字以在每个通道上形成适当的输出。每个输出由一组八个电流源组成，四个具有一个极性的电流，另外四个具有与电流相反的极性。在四组中，目前的来源是二次相关的，I，2I，4I和8I。在这种布置中，每个通道可以提供16个振幅乘以两个极性的电流; 意味着32个当前水平。该通道只是一个5位数模转换器。输出电路包含电荷平衡开关。这些开关设计用于在电流源关闭时恢复剩余电荷。如果过量电荷太大，它们也被设计为充电恢复期间的电流极限，以免它们不会引起神经损伤。每个通道的电荷平衡（不会通过直流电流或充电）和充电限制，以防止电极损坏和骨骼生长。电荷平衡由电荷平衡开关和阻塞电容进行。电荷限制仅由阻塞电容器执行。每个通道的充电电平使用组合多个并联的开关的开关网络梯形图来定义; 每个开关的闭合将从先前的开关切换出的当前电平加倍。

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