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1. 发明授权

US09864682B2 Nonvolatile memory device and storage device having the same and operation method thereof 有权
公开(公告)号：US09864682B2
公开(公告)日：2018-01-09
申请号：US14664125
申请日：2015-03-20
申请人： Doohyun Kim , BoGeun Kim , Kitae Park , Jinman Han
发明人： Doohyun Kim , BoGeun Kim , Kitae Park , Jinman Han
IPC分类号： G06F12/02 , G11C11/56 , G11C16/04
CPC分类号： G06F12/0246 , G06F2212/7201 , G11C11/5621 , G11C16/0483
摘要： According to example embodiments, a method of operating a storage device includes reading a process capability index using a memory controller, adjusting at least one operation condition based on the process capability index, and operating one of at least one nonvolatile memory device according to the at least one operation condition adjusted. The process capability index indicates how a structure associated with a memory cell to be operated deviates from a target shape.

2. 发明授权

US08976587B2 Data storage system having multi-bit memory device and operating method thereof 有权
标题翻译：具有多位存储装置的数据存储系统及其操作方法
公开(公告)号：US08976587B2
公开(公告)日：2015-03-10
申请号：US13737140
申请日：2013-01-09
申请人： Sangyong Yoon , Kitae Park , Jinman Han , Wonseok Lee
发明人： Sangyong Yoon , Kitae Park , Jinman Han , Wonseok Lee
IPC分类号： G11C16/04 , G11C16/10 , G11C11/56 , G11C16/26 , G11C14/00
CPC分类号： G11C16/10 , G11C11/56 , G11C11/5628 , G11C14/0018 , G11C16/0483 , G11C16/26 , G11C2211/5641 , G11C2211/5642 , G11C2211/5643
摘要： The operating method of a data storage device includes storing data in a buffer memory according to an external request, and determining whether the data stored in the buffer memory is data accompanying a buffer program operation of a memory cell array. When the data stored in the buffer memory is data accompanying the buffer program operation, the method further includes determining whether a main program operation on the memory cell array is required, and when a main program operation on the memory cell array is required, determining a program pattern of the main program operation on the memory cell array. The method further includes issuing a set of commands for the main program operation on the memory cell array to a multi-bit memory device based on the determined program pattern.
摘要翻译：数据存储装置的操作方法包括根据外部请求将数据存储在缓冲存储器中，并且确定存储在缓冲存储器中的数据是否是伴随存储器单元阵列的缓冲器程序操作的数据。当存储在缓冲存储器中的数据是与缓冲器程序操作相关的数据时，该方法还包括确定是否需要对存储单元阵列的主程序操作，以及当需要存储单元阵列的主程序操作时，存储单元阵列中的主程序操作的程序模式。该方法还包括基于所确定的程序模式向存储器单元阵列发出用于主程序操作的一组命令到多位存储器件。

3. 发明授权

US08812933B2 Memory system and operating method thereof 有权
标题翻译：存储系统及其操作方法
公开(公告)号：US08812933B2
公开(公告)日：2014-08-19
申请号：US13449501
申请日：2012-04-18
申请人： Sang-Hyun Joo , Kitae Park , Sangyong Yoon , Jinman Han
发明人： Sang-Hyun Joo , Kitae Park , Sangyong Yoon , Jinman Han
IPC分类号： G06F11/00 , G11C29/00 , H03M13/00 , G11C11/34 , G11C8/00 , G06F11/10 , G06F11/08 , H03M13/15
CPC分类号： G06F11/1016 , G06F11/08 , G06F11/10 , G06F11/1008 , G06F11/1048 , G06F11/1068 , G06F11/1076 , G06F11/108 , G11C11/5628 , G11C16/10 , G11C16/3418 , H03M13/151 , H03M13/1525 , H03M13/1545
摘要： A memory system includes a nonvolatile memory device and a memory controller configured to control the nonvolatile memory device and configured to provide the nonvolatile memory device with error flag information including error location information of an error of data read from the nonvolatile memory device.
摘要翻译：存储器系统包括非易失性存储器件和存储器控制器，其被配置为控制非易失性存储器件并且被配置为向非易失性存储器件提供包括从非易失性存储器件读取的数据的错误的错误位置信息的错误标志信息。

4. 发明申请

US20100315876A1 MEMORY DEVICES AND OPERATIONS THEREOF USING PROGRAM STATE DETERMINATION BASED ON DATA VALUE DISTRIBUTION 有权
标题翻译：使用基于数据值分配的程序状态确定的存储器件和操作
公开(公告)号：US20100315876A1
公开(公告)日：2010-12-16
申请号：US12748113
申请日：2010-03-26
申请人： Kitae Park , Jinman Han
发明人： Kitae Park , Jinman Han
IPC分类号： G11C16/34
CPC分类号： G11C16/26
摘要： In a memory device, a proportion of at least one cell state in a unit of the memory is determined. A program state of the unit of the memory is determined based on the determined proportion of the at least one cell state. Determining a proportion of at least one cell state in a unit of the memory may be preceded by processing data to be stored in the unit of the memory according to a data value distribution function to produce transformed data having data values conforming to a predetermined distribution and storing the transformed data in the unit of the memory. The distribution function may be configured, for example, to provide a uniform distribution of data values in the unit of the memory.
摘要翻译：在存储器装置中，确定存储器单元中至少一个单元状态的比例。基于确定的至少一个小区状态的比例来确定存储器单元的编程状态。确定存储器单元中至少一个单元状态的比例之前可以根据数据值分布函数处理存储在存储器单元中的数据，以产生具有符合预定分布的数据值的变换数据，以及将变换的数据存储在存储器的单元中。分配功能可以被配置为例如以存储器为单位提供数据值的均匀分布。

5. 发明授权

US08284603B2 Memory devices and operations thereof using program state determination based on data value distribution 有权
标题翻译：使用基于数据值分布的程序状态确定的存储器件及其操作
公开(公告)号：US08284603B2
公开(公告)日：2012-10-09
申请号：US12748113
申请日：2010-03-26
申请人： Kitae Park , Jinman Han
发明人： Kitae Park , Jinman Han
IPC分类号： G11C11/34
CPC分类号： G11C16/26
摘要： In a memory device, a proportion of at least one cell state in a unit of the memory is determined. A program state of the unit of the memory is determined based on the determined proportion of the at least one cell state. Determining a proportion of at least one cell state in a unit of the memory may be preceded by processing data to be stored in the unit of the memory according to a data value distribution function to produce transformed data having data values conforming to a predetermined distribution and storing the transformed data in the unit of the memory. The distribution function may be configured, for example, to provide a uniform distribution of data values in the unit of the memory.
摘要翻译：在存储器装置中，确定存储器单元中至少一个单元状态的比例。基于确定的至少一个小区状态的比例来确定存储器单元的编程状态。确定存储器单元中的至少一个单元状态的比例之前可以根据数据值分布函数处理要存储在存储器单元中的数据，以产生具有符合预定分布的数据值的变换数据，以及将变换的数据存储在存储器的单元中。分配功能可以被配置为例如以存储器为单位提供数据值的均匀分布。

6. 发明申请

US20110222342A1 DATA STORAGE SYSTEM HAVING MULTI-BIT MEMORY DEVICE AND OPERATING METHOD THEREOF 有权
标题翻译：具有多位存储器件的数据存储系统及其操作方法
公开(公告)号：US20110222342A1
公开(公告)日：2011-09-15
申请号：US13040295
申请日：2011-03-04
申请人： Sangyong Yoon , Kitae Park , Jinman Han , Wonseok Lee
发明人： Sangyong Yoon , Kitae Park , Jinman Han , Wonseok Lee
IPC分类号： G11C16/10 , G11C16/04
CPC分类号： G11C16/10 , G11C11/56 , G11C11/5628 , G11C14/0018 , G11C16/0483 , G11C16/26 , G11C2211/5641 , G11C2211/5642 , G11C2211/5643
摘要： A data storage device includes a non-volatile memory device which includes a memory cell array; and a memory controller which includes a buffer memory and which controls the non-volatile memory device. The operating method of the data storage device includes storing data in the buffer memory according to an external request, and determining whether the data stored in the buffer memory is data accompanying a buffer program operation of the memory cell array. When the data stored in the buffer memory is data accompanying the buffer program operation, the method further includes determining whether a main program operation on the memory cell array is required, and when a main program operation on the memory cell array is required, determining a program pattern of the main program operation on the memory cell array. The method further includes issuing a set of commands for the main program operation on the memory cell array to the multi-bit memory device based on the determined program pattern.
摘要翻译：数据存储装置包括：非易失性存储装置，其包括存储单元阵列; 以及包括缓冲存储器并且控制非易失性存储器件的存储器控制器。数据存储装置的操作方法包括根据外部请求将数据存储在缓冲存储器中，并且确定存储在缓冲存储器中的数据是否是与存储单元阵列的缓冲器程序操作相关的数据。当存储在缓冲存储器中的数据是伴随缓冲器程序操作的数据时，该方法还包括确定是否需要对存储单元阵列执行主程序操作，并且当需要存储单元阵列的主程序操作时，存储单元阵列中的主程序操作的程序模式。该方法还包括基于所确定的程序模式向存储器单元阵列发出用于主程序操作的一组命令给多位存储器件。

7. 发明申请

US20130141972A1 DATA STORAGE SYSTEM HAVING MULTI-BIT MEMORY DEVICE AND OPERATING METHOD THEREOF 有权
标题翻译：具有多位存储器件的数据存储系统及其操作方法
公开(公告)号：US20130141972A1
公开(公告)日：2013-06-06
申请号：US13737140
申请日：2013-01-09
申请人： Sangyong Yoon , Kitae Park , Jinman Han , Wonseok Lee
发明人： Sangyong Yoon , Kitae Park , Jinman Han , Wonseok Lee
IPC分类号： G11C16/10 , G11C16/26
CPC分类号： G11C16/10 , G11C11/56 , G11C11/5628 , G11C14/0018 , G11C16/0483 , G11C16/26 , G11C2211/5641 , G11C2211/5642 , G11C2211/5643
摘要： A data storage device includes a non-volatile memory device which includes a memory cell array; and a memory controller which includes a buffer memory and which controls the non-volatile memory device. The operating method of the data storage device includes storing data in the buffer memory according to an external request, and determining whether the data stored in the buffer memory is data accompanying a buffer program operation of the memory cell array. When the data stored in the buffer memory is data accompanying the buffer program operation, the method further includes determining whether a main program operation on the memory cell array is required, and when a main program operation on the memory cell array is required, determining a program pattern of the main program operation on the memory cell array. The method further includes issuing a set of commands for the main program operation on the memory cell array to the multi-bit memory device based on the determined program pattern.
摘要翻译：数据存储装置包括：非易失性存储装置，其包括存储单元阵列; 以及包括缓冲存储器并且控制非易失性存储器件的存储器控制器。数据存储装置的操作方法包括根据外部请求将数据存储在缓冲存储器中，并且确定存储在缓冲存储器中的数据是否是与存储单元阵列的缓冲器程序操作相关的数据。当存储在缓冲存储器中的数据是与缓冲器程序操作相关的数据时，该方法还包括确定是否需要对存储单元阵列的主程序操作，以及当需要存储单元阵列的主程序操作时，存储单元阵列中的主程序操作的程序模式。该方法还包括基于所确定的程序模式向存储器单元阵列发出用于主程序操作的一组命令给多位存储器件。

8. 发明授权

US08305817B2 Nonvolatile memory devices and program methods thereof in which a target verify operation and a pre-pass verify operation are performed simultaneously using a common verify voltage 有权
标题翻译：其中使用公共验证电压同时执行目标验证操作和预通过验证操作的非易失性存储器件及其编程方法
公开(公告)号：US08305817B2
公开(公告)日：2012-11-06
申请号：US12722056
申请日：2010-03-11
申请人： Kitae Park , Donghyuk Chae , Jinman Han
发明人： Kitae Park , Donghyuk Chae , Jinman Han
IPC分类号： G11C16/06
CPC分类号： G11C11/5628 , G11C16/10 , G11C16/3459 , G11C2211/5621
摘要： Provided are nonvolatile memory devices and program methods thereof. A nonvolatile memory device provides a program voltage to a selected word line and performs a program verify operation. The nonvolatile memory device controls a bit line voltage of the next program loop according to the program verification result. In the program verification operation, a target verify voltage is used as a pre-verify voltage. The nonvolatile memory device controls the bit line voltage of the next program loop according to the program verification result, thus making it possible to reduce the threshold voltage distribution of a memory cell. Also, the nonvolatile memory device uses the target verify voltage as the pre-verify voltage, thus making it possible to increase the program verification speed.
摘要翻译：提供了非易失性存储器件及其编程方法。非易失性存储器件向所选字线提供编程电压，并执行程序验证操作。非易失性存储器件根据程序验证结果控制下一个程序循环的位线电压。在程序验证操作中，使用目标验证电压作为预验证电压。非易失性存储器件根据程序验证结果控制下一个程序循环的位线电压，从而可以减小存储单元的阈值电压分布。此外，非易失性存储器件使用目标验证电压作为预验证电压，从而可以增加程序验证速度。

9. 发明申请

US20110075478A1 NONVOLATILE MEMORY DEVICE AND SYSTEM, AND METHOD OF PROGRAMMING A NONVOLATILE MEMORY DEVICE 有权
标题翻译：非易失性存储器件和系统，以及编程非易失性存储器件的方法
公开(公告)号：US20110075478A1
公开(公告)日：2011-03-31
申请号：US12882378
申请日：2010-09-15
申请人： Sangyong Yoon , Jinman Han , Kitae Park , Joon Young Kwak
发明人： Sangyong Yoon , Jinman Han , Kitae Park , Joon Young Kwak
IPC分类号： G11C16/06 , G11C16/04
CPC分类号： G11C11/5628 , G06F11/1072 , G11C11/10
摘要： A nonvolatile memory includes a plurality of N-bit multi-level cell (MLC) memory cells and a controller. The plurality of N-bit MLC memory cells are for storing N pages of data, each of the MLC memory cells programmable into any one of 2N threshold voltage distributions, where N is a positive number. The controller is configured to program the N pages of data into the MLC memory cells, and to execute a partial interleave process in which the N pages of data are divided into M page groups, where M is a positive number and where each page group includes at least one of the N pages of data, and in which each of the M page groups is applied to an error correction code (ECC) circuit to generate parity bits for the respective M page groups, where a bit-error rate (BER) among the pages within each of the M groups is equalized by the partial interleave process
摘要翻译：非易失性存储器包括多个N位多电平单元（MLC）存储器单元和控制器。多个N位MLC存储器单元用于存储N页数据，MLC存储单元中的每一个可编程为2N个阈值电压分布中的任何一个，其中N是正数。控制器被配置为将N页数据编程到MLC存储器单元中，并且执行部分交错处理，其中N页数据被划分为M页组，其中M是正数，并且每个页组包括 N页数据中的至少一个，并且其中M页组中的每一个被应用于纠错码（ECC）电路以产生各个M页组的奇偶校验位，其中误码率（BER）在每个M组内的页面之间通过部分交错处理来均衡

10. 发明申请

US20110007571A1 NONVOLATILE MEMORY DEVICES AND PROGRAM METHODS THEREOF IN WHICH A TARGET VERIFY OPERATION AND A PRE-PASS VERIFY OPERATION ARE PERFORMED SIMULTANEOUSLY USING A COMMON VERIFY VOLTAGE 有权
标题翻译：非易失性存储器件及其程序方法，其目标验证操作和预编译操作同时使用常见的验证电压执行
公开(公告)号：US20110007571A1
公开(公告)日：2011-01-13
申请号：US12722056
申请日：2010-03-11
申请人： Kitae Park , Donghyuk Chae , Jinman Han
发明人： Kitae Park , Donghyuk Chae , Jinman Han
IPC分类号： G11C16/06
CPC分类号： G11C11/5628 , G11C16/10 , G11C16/3459 , G11C2211/5621
摘要： Provided are nonvolatile memory devices and program methods thereof. A nonvolatile memory device provides a program voltage to a selected word line and performs a program verify operation. The nonvolatile memory device controls a bit line voltage of the next program loop according to the program verification result. In the program verification operation, a target verify voltage is used as a pre-verify voltage. The nonvolatile memory device controls the bit line voltage of the next program loop according to the program verification result, thus making it possible to reduce the threshold voltage distribution of a memory cell. Also, the nonvolatile memory device uses the target verify voltage as the pre-verify voltage, thus making it possible to increase the program verification speed.
摘要翻译：提供了非易失性存储器件及其编程方法。非易失性存储器件向所选字线提供编程电压，并执行程序验证操作。非易失性存储器件根据程序验证结果控制下一个程序循环的位线电压。在程序验证操作中，使用目标验证电压作为预验证电压。非易失性存储器件根据程序验证结果控制下一个程序循环的位线电压，从而可以减小存储单元的阈值电压分布。此外，非易失性存储器件使用目标验证电压作为预验证电压，从而可以增加程序验证速度。

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