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1. 发明授权

US6052025A CMOS operational amplifiers having reduced power consumption requirements and improved phase margin characteristics 失效
标题翻译： CMOS运算放大器具有降低的功耗要求和改进的相位裕度特性
公开(公告)号：US6052025A
公开(公告)日：2000-04-18
申请号：US124599
申请日：1998-07-29
申请人： Dong-Young Chang , You-Mi Lee , Seung-Hoon Lee , Geun-Soon Kang , Hee-Cheol Choi
发明人： Dong-Young Chang , You-Mi Lee , Seung-Hoon Lee , Geun-Soon Kang , Hee-Cheol Choi
IPC分类号： H01L21/8234 , H01L27/088 , H03F3/45
CPC分类号： H03F3/45219 , H03F3/45654 , H03F2203/45398
摘要： Operational amplifier integrated circuits include a differential input stage, a cascode current mirror, a cascode current source and a preferred bias signal generator which is responsive to a clock signal and is electrically coupled to the differential input stage, the cascode current mirror and the cascode current source. This preferred bias signal generator sequentially enables the cascode current mirror and then the differential input stage in response to a rising edge of the clock signal and disables the cascode current mirror and the cascode current source in response to a falling edge of the clock signal. This sequential enablement of the cascode current mirror before the differential input stage improves the unity gain phase margin characteristics of the circuit and the disablement of the cascode current mirror and the cascode current source in response to the falling edge of the clock signal decreases the power consumption requirements of the circuit.
摘要翻译：运算放大器集成电路包括差分输入级，共源共栅电流镜，共源共栅电流源和优选的偏置信号发生器，其响应于时钟信号并电耦合到差分输入级，共源共栅电流镜和共源共栅电流资源。该优选的偏置信号发生器响应于时钟信号的上升沿而依次启用共源共栅电流镜和差分输入级，并响应时钟信号的下降沿禁用共源共栅电流反射镜和共源共栅电流源。在差分输入级之前，级联电流镜的这种顺序启用提高了电路的单位增益相位裕度特性，并且响应于时钟信号的下降沿，共源共栅电流反射镜和共源共栅电流源的禁用降低了功耗电路要求。

2. 发明申请

US20050152200A1 Semiconductor memory having variable memory size and method for refreshing the same 有权
标题翻译：具有可变存储器大小的半导体存储器及其刷新方法
公开(公告)号：US20050152200A1
公开(公告)日：2005-07-14
申请号：US10928191
申请日：2004-08-30
申请人： You-Mi Lee , Kyung-Woo Nam
发明人： You-Mi Lee , Kyung-Woo Nam
IPC分类号： G11C11/401 , G11C7/10 , G11C11/406 , G11C7/00
CPC分类号： G11C11/40622 , G11C7/1045 , G11C11/406
摘要： A semiconductor memory device is operable in a full capacity mode and at least one reduced capacity mode, and includes a memory array having a plurality of memory blocks, each of the memory blocks having at least one word line. An address generation circuit generates a first multi-bit address signal having a logic value which is sequentially incremented by one during each of successive refresh periods. An address sorting circuit receives the first multi-bit address signal and outputs a second multi-bit address signal in which one or more least significant bits of the first multi-bit address signal are arranged in the second multi-bit address signal to indicate a memory block of the memory array, and in which remaining bits of the first multi-bit address signal are arranged in the second multi-bit address to indicate a word line within the selected memory block. The word lines of the memory array are refreshed according to the second multi-bit address signal.
摘要翻译：半导体存储器件可在全容量模式和至少一个简化容量模式下操作，并且包括具有多个存储块的存储器阵列，每个存储器块具有至少一个字线。地址产生电路产生具有逻辑值的第一多位地址信号，该逻辑值在每个连续刷新周期期间依次递增1。地址分类电路接收第一多位地址信号并输出第二多位地址信号，其中第一多位地址信号的一个或多个最低有效位被布置在第二多位地址信号中以指示第存储器阵列的存储块，并且其中第一多位地址信号的剩余位被布置在第二多位地址中以指示所选存储块内的字线。存储器阵列的字线根据第二多位地址信号被刷新。

3. 发明授权

US07095670B2 Semiconductor memory having variable memory size and method for refreshing the same 有权
标题翻译：具有可变存储器大小的半导体存储器及其刷新方法
公开(公告)号：US07095670B2
公开(公告)日：2006-08-22
申请号：US10928191
申请日：2004-08-30
申请人： You-Mi Lee , Kyung-Woo Nam
发明人： You-Mi Lee , Kyung-Woo Nam
IPC分类号： G11C7/00
CPC分类号： G11C11/40622 , G11C7/1045 , G11C11/406
摘要： A semiconductor memory device is operable in a full capacity mode and at least one reduced capacity mode, and includes a memory array having a plurality of memory blocks, each of the memory blocks having at least one word line. An address generation circuit generates a first multi-bit address signal having a logic value which is sequentially incremented by one during each of successive refresh periods. An address sorting circuit receives the first multi-bit address signal and outputs a second multi-bit address signal in which one or more least significant bits of the first multi-bit address signal are arranged in the second multi-bit address signal to indicate a memory block of the memory array, and in which remaining bits of the first multi-bit address signal are arranged in the second multi-bit address to indicate a word line within the selected memory block. The word lines of the memory array are refreshed according to the second multi-bit address signal.
摘要翻译：半导体存储器件可在全容量模式和至少一个简化容量模式下操作，并且包括具有多个存储块的存储器阵列，每个存储器块具有至少一个字线。地址产生电路产生具有逻辑值的第一多位地址信号，该逻辑值在每个连续刷新周期期间依次递增1。地址分类电路接收第一多位地址信号并输出第二多位地址信号，其中第一多位地址信号的一个或多个最低有效位被布置在第二多位地址信号中以指示第存储器阵列的存储块，并且其中第一多位地址信号的剩余位被布置在第二多位地址中以指示所选存储块内的字线。存储器阵列的字线根据第二多位地址信号被刷新。

4. 发明授权

US07518409B2 Input stage of semiconductor device with multiple pads of common function, and multi-chip package having the same 失效
标题翻译：具有多个共同功能焊盘的半导体器件的输入级，以及具有相同功能的多芯片封装
公开(公告)号：US07518409B2
公开(公告)日：2009-04-14
申请号：US11352175
申请日：2006-02-10
申请人： You-Mi Lee , Woo-Seop Jeong
发明人： You-Mi Lee , Woo-Seop Jeong
IPC分类号： H01L25/00
CPC分类号： H01L23/49575 , H01L24/45 , H01L24/48 , H01L2224/32245 , H01L2224/451 , H01L2224/48091 , H01L2224/48247 , H01L2224/73265 , H01L2924/00014 , H01L2924/13091 , H01L2924/1532 , H01L2924/181 , H01L2924/00 , H01L2924/00015 , H01L2224/05599 , H01L2924/00012
摘要： An input stage of a semiconductor device includes at least two pads, input buffers, a current source, and a logic operation circuit. The at least two pads, to which the input buffers respectively correspond, perform a common function. The current source provides a current to the respective at least two pads so that a predetermined fixed logic value is outputted by the input buffers while the respective at least two pads have a floating status. The logic operation circuit performs a logic operation on signals applied to the respective at least two pads via the input buffers, and outputs a resultant value to an internal circuit. When the input end of the semiconductor is used in a multi-chip package, the internal circuit may not be affected by the other pads that are not bonded to external pins, even though only one pad is bonded to an external pin.
摘要翻译：半导体器件的输入级包括至少两个焊盘，输入缓冲器，电流源和逻辑运算电路。输入缓冲器分别对应的至少两个焊盘执行共同的功能。电流源向相应的至少两个焊盘提供电流，使得预定的固定逻辑值由输入缓冲器输出，而相应的至少两个焊盘具有浮动状态。逻辑运算电路经由输入缓冲器对施加到相应的至少两个焊盘的信号执行逻辑运算，并将结果值输出到内部电路。当半导体的输入端用于多芯片封装时，即使只有一个焊盘接合到外部引脚，内部电路也可能不会受到其他焊盘的影响。

5. 发明申请

US20060180913A1 Input stage of semiconductor device with multiple pads of common function, and multi-chip package having the same 失效
公开(公告)号：US20060180913A1
公开(公告)日：2006-08-17
申请号：US11352175
申请日：2006-02-10
申请人： You-Mi Lee , Woo-Seop Jeong
发明人： You-Mi Lee , Woo-Seop Jeong
IPC分类号： H01L23/02
CPC分类号： H01L23/49575 , H01L24/45 , H01L24/48 , H01L2224/32245 , H01L2224/451 , H01L2224/48091 , H01L2224/48247 , H01L2224/73265 , H01L2924/00014 , H01L2924/13091 , H01L2924/1532 , H01L2924/181 , H01L2924/00 , H01L2924/00015 , H01L2224/05599 , H01L2924/00012
摘要： An input stage of a semiconductor device includes at least two pads, input buffers, a current source, and a logic operation circuit. The at least two pads, to which the input buffers respectively correspond, perform a common function. The current source provides a current to the respective at least two pads so that a predetermined fixed logic value is outputted by the input buffers while the respective at least two pads have a floating status. The logic operation circuit performs a logic operation on signals applied to the respective at least two pads via the input buffers, and outputs a resultant value to an internal circuit. When the input end of the semiconductor is used in a multi-chip package, the internal circuit may not be affected by the other pads that are not bonded to external pins, even though only one pad is bonded to an external pin.

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