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1. 发明授权

US06512244B1 SOI device with structure for enhancing carrier recombination and method of fabricating same 有权
标题翻译：具有用于增强载流子复合的结构的SOI器件及其制造方法
公开(公告)号：US06512244B1
公开(公告)日：2003-01-28
申请号：US09850392
申请日：2001-05-07
申请人： Dong-Hyuk Ju , William G. En , Srinath Krishnan , Xilin Judy An
发明人： Dong-Hyuk Ju , William G. En , Srinath Krishnan , Xilin Judy An
IPC分类号： H01L2120
CPC分类号： H01L29/66772 , H01L29/78612 , H01L29/78621
摘要： A semiconductor-on-insulator (SOI) device. The SOI device includes an SOI wafer including an active layer, a substrate and a buried insulation layer disposed therebetween. The active layer includes an abrupt region disposed along a lower portion of the active layer, the abrupt region having the same P or N doping type as a doping type of a body region.
摘要翻译：绝缘体上半导体（SOI）器件。 SOI器件包括SOI晶片，其包括有源层，衬底和设置在其间的掩埋绝缘层。有源层包括沿有源层的下部布置的突变区域，突变区域具有与体区域的掺杂类型相同的P或N掺杂类型。

2. 发明授权

US07122863B1 SOI device with structure for enhancing carrier recombination and method of fabricating same 有权
标题翻译：具有用于增强载流子复合的结构的SOI器件及其制造方法
公开(公告)号：US07122863B1
公开(公告)日：2006-10-17
申请号：US09850393
申请日：2001-05-07
申请人： Dong-Hyuk Ju , William G. En , Srinath Krishnan , Xilin Judy An
发明人： Dong-Hyuk Ju , William G. En , Srinath Krishnan , Xilin Judy An
IPC分类号： H01L27/01
CPC分类号： H01L29/78612 , H01L29/78696
摘要： A semiconductor-on-insulator (SOI) device. The SOI device includes an SOI wafer including an active layer, a substrate and a buried insulation layer disposed therebetween. The buried insulation layer includes an oxide trap region disposed along an upper surface of the buried insulation layer, the oxide trap region having a plurality of oxide traps to promote carrier recombination.
摘要翻译：绝缘体上半导体（SOI）器件。 SOI器件包括SOI晶片，其包括有源层，衬底和设置在其间的掩埋绝缘层。掩埋绝缘层包括沿着掩埋绝缘层的上表面设置的氧化物陷阱区，氧化物阱区具有多个氧化物陷阱以促进载流子复合。

3. 发明授权

US06713819B1 SOI MOSFET having amorphized source drain and method of fabrication 失效
标题翻译：具有非晶化源极漏极和制造方法的SOI MOSFET
公开(公告)号：US06713819B1
公开(公告)日：2004-03-30
申请号：US10118364
申请日：2002-04-08
申请人： William G. En , Dong-Hyuk Ju , Srinath Krishnan
发明人： William G. En , Dong-Hyuk Ju , Srinath Krishnan
IPC分类号： H01L2976
CPC分类号： H01L29/78609 , H01L21/84 , H01L27/1203 , H01L29/78612
摘要： An integrated circuit formed in semiconductor-on-insulator format. The integrated circuit includes a layer of semiconductor material disposed on an insulating layer, where the insulating layer disposed on a substrate. A first and a second MOSFET are provided such that one of a source and a drain of the first MOSFET is disposed adjacent one of a source and a drain of the second MOSFET. An amorphous region is formed in the layer of semiconductor material and extending from an upper surface of the layer of semiconductor material to the isolation layer. The amorphous region is formed between a crystalline portion of the one of the source and the drain of the first MOSFET and a crystalline portion of the one of the source and the drain of the second MOSFET.
摘要翻译：一种以绝缘体半导体形式形成的集成电路。集成电路包括设置在绝缘层上的半导体材料层，其中设置在基板上的绝缘层。提供第一和第二MOSFET，使得第一MOSFET的源极和漏极中的一个被设置为邻近第二MOSFET的源极和漏极之一。在半导体材料层中形成非晶区域并从半导体材料层的上表面延伸到隔离层。非晶区域形成在第一MOSFET的源极和漏极之一的结晶部分和第二MOSFET的源极和漏极之一的结晶部分之间。

4. 发明授权

US06535015B1 Device and method for testing performance of silicon structures 有权
标题翻译：用于测试硅结构性能的器件和方法
公开(公告)号：US06535015B1
公开(公告)日：2003-03-18
申请号：US09845266
申请日：2001-04-30
申请人： Srinath Krishnan , Dong-Hyuk Ju , William G. En , Siu Lun Lee , Richard K. Klein
发明人： Srinath Krishnan , Dong-Hyuk Ju , William G. En , Siu Lun Lee , Richard K. Klein
IPC分类号： G01R3102
CPC分类号： G01R31/2884
摘要： An integrated test circuit for a silicon on insulator circuit structure is formed on the same wafer as the circuit structure. The wafer includes an input circuit coupled to the silicon on insulator circuit structure which generates a drive signal for operating the silicon on insulator circuit structure and an output circuit which processes a response signal from the circuit structure to generate an output signal representing certain characteristics of the silicon on insulator circuit structure.
摘要翻译：用于绝缘体上硅电路结构的集成测试电路形成在与电路结构相同的晶片上。晶片包括耦合到绝缘体上硅电路结构的输入电路，其产生用于操作绝缘体上硅电路结构的驱动信号，以及输出电路，其处理来自电路结构的响应信号，以产生表示某些特性的输出信号硅绝缘体电路结构。

5. 发明授权

US06566213B2 Method of fabricating multi-thickness silicide device formed by disposable spacers 失效
标题翻译：制造由一次性间隔物形成的多层硅化物装置的方法
公开(公告)号：US06566213B2
公开(公告)日：2003-05-20
申请号：US09824123
申请日：2001-04-02
申请人： William G. En , Srinath Krishnan , Dong-Hyuk Ju , Bin Yu
发明人： William G. En , Srinath Krishnan , Dong-Hyuk Ju , Bin Yu
IPC分类号： H01L21336
CPC分类号： H01L29/66507 , H01L21/28518 , H01L21/823443 , H01L29/41733 , H01L29/458 , H01L29/6653 , H01L29/66772 , H01L29/78621
摘要： A transistor device formed on a semiconductor-on-insulator (SOI) substrate with a buried oxide (BOX) layer disposed thereon and an active layer disposed on the BOX layer having active regions defined by isolation trenches. The device includes a gate defining a channel interposed between a source and a drain formed within the active region of the SOI substrate. Further, the device includes a plurality of thin silicide layers formed on the source and the drain. Additionally, at least an upper silicide layer of the plurality of thin silicide layers extends beyond a lower silicide layer. Further still, the device includes a disposable spacer used in the formation of the device. The device further includes a second plurality of thin silicide layers formed on a polysilicon electrode of the gate.
摘要翻译：一种在绝缘体上半导体（SOI）衬底上形成的埋置氧化物（BOX）层的晶体管器件，以及设置在具有由隔离沟槽限定的有源区域的BOX层上的有源层。该器件包括限定插入在SOI衬底的有源区域内形成的源极和漏极之间的沟道的栅极。此外，该器件包括形成在源极和漏极上的多个薄硅化物层。另外，多个薄硅化物层中的至少一个上硅化物层延伸超过下硅化物层。此外，该装置还包括用于形成装置的一次性间隔件。该器件还包括形成在栅极的多晶硅电极上的第二多个薄硅化物层。

6. 发明授权

US06548361B1 SOI MOSFET and method of fabrication 有权
标题翻译： SOI MOSFET及其制造方法
公开(公告)号：US06548361B1
公开(公告)日：2003-04-15
申请号：US10145915
申请日：2002-05-15
申请人： William G. En , Dong-Hyuk Ju , Srinath Krishnan
发明人： William G. En , Dong-Hyuk Ju , Srinath Krishnan
IPC分类号： H01L21336
CPC分类号： H01L29/78696 , H01L21/26506 , H01L29/6656 , H01L29/66772 , H01L29/78612 , H01L29/78621
摘要： A MOSFET formed in semiconductor-on-insulator format. The MOSFET includes a source and a drain formed in a layer of semiconductor material, each having an extension region and a deep doped region. A body is formed between the source and the drain and includes a first damaged region adjacent the extension of the source and a second damaged region adjacent the extension of the drain. The first and second damaged regions include defects caused by amorphization of the layer of semiconductor material. A gate electrode, the source, the drain and the body are operatively arranged to form a transistor.
摘要翻译：以半导体绝缘体形式形成的MOSFET。 MOSFET包括形成在半导体材料层中的源极和漏极，每个具有延伸区域和深度掺杂区域。主体形成在源极和漏极之间，并且包括邻近源的延伸部的第一损坏区域和邻近漏极延伸部的第二损坏区域。第一和第二受损区域包括由半导体材料层的非晶化引起的缺陷。栅电极，源极，漏极和主体被可操作地布置以形成晶体管。

7. 发明授权

US06441433B1 Method of making a multi-thickness silicide SOI device 失效
标题翻译：制造多层硅化物SOI器件的方法
公开(公告)号：US06441433B1
公开(公告)日：2002-08-27
申请号：US09824412
申请日：2001-04-02
申请人： William G. En , Srinath Krishnan , Dong-Hyuk Ju , Bin Yu
发明人： William G. En , Srinath Krishnan , Dong-Hyuk Ju , Bin Yu
IPC分类号： H01L3113
CPC分类号： H01L29/66507 , H01L21/28518 , H01L29/41733 , H01L29/458 , H01L29/6653 , H01L29/6656 , H01L29/66772 , H01L29/78603 , H01L29/78621 , H01L2924/0002 , H01L2924/00
摘要： A transistor device formed on a semiconductor-on-insulator (SOI) substrate with a buried oxide (BOX) layer disposed thereon and an active layer disposed on the BOX layer having active regions defined by isolation trenches. The device includes a gate defining a channel interposed between a source and a drain formed within the active region of the SOI substrate. Further, the device includes a multi-thickness silicide layer formed on the main source and drain regions and source and drain extension regions wherein a portion of the multi-thickness silicide layer which is formed on the source and drain extension regions is thinner than a portion of the silicide layer which is formed on the main source and drain regions. The device further includes a second thin silicide layer formed on a polysilicon electrode of the gate.
摘要翻译：一种在绝缘体上半导体（SOI）衬底上形成的埋置氧化物（BOX）层的晶体管器件，以及设置在具有由隔离沟槽限定的有源区域的BOX层上的有源层。该器件包括限定插入在SOI衬底的有源区域内形成的源极和漏极之间的沟道的栅极。此外，器件包括形成在主源极和漏极区域以及源极和漏极延伸区域上的多层硅化物层，其中形成在源极和漏极延伸区域上的多层硅化物层的一部分比部分形成在主源极和漏极区上的硅化物层。该器件还包括形成在栅极的多晶硅电极上的第二薄硅化物层。

8. 发明授权

US06518631B1 Multi-Thickness silicide device formed by succesive spacers 有权
标题翻译：由连续间隔件形成的多层硅化物器件
公开(公告)号：US06518631B1
公开(公告)日：2003-02-11
申请号：US09824418
申请日：2001-04-02
申请人： William G. En , Srinath Krishnan , Dong-Hyuk Ju , Bin Yu
发明人： William G. En , Srinath Krishnan , Dong-Hyuk Ju , Bin Yu
IPC分类号： H01L31113
CPC分类号： H01L29/6653 , H01L29/41733 , H01L29/458 , H01L29/66772 , H01L29/78603 , H01L29/78621
摘要： A transistor device formed on a semiconductor-on-insulator (SOI) substrate with a buried oxide (BOX) layer disposed thereon and an active layer disposed on the BOX layer having active regions defined by isolation trenches. The device includes a gate defining a channel interposed between a source and a drain formed within the active region of the SOI substrate. Further, the device includes a plurality of thin silicide layers formed on the source and the drain. Additionally, at least an upper silicide layer of the plurality of thin silicide layers extends beyond a lower silicide layer. Further still, the device includes a plurality of spacers used in the formation of the device. The device further includes a second plurality of thin silicide layers formed on a polysilicon electrode of the gate.
摘要翻译：一种在绝缘体上半导体（SOI）衬底上形成的埋置氧化物（BOX）层的晶体管器件，以及设置在具有由隔离沟槽限定的有源区域的BOX层上的有源层。该器件包括限定插入在SOI衬底的有源区域内形成的源极和漏极之间的沟道的栅极。此外，该器件包括形成在源极和漏极上的多个薄硅化物层。另外，多个薄硅化物层中的至少一个上硅化物层延伸超过下硅化物层。此外，该装置还包括用于形成装置的多个间隔物。该器件还包括形成在栅极的多晶硅电极上的第二多个薄硅化物层。

9. 发明授权

US07253068B1 Dual SOI film thickness for body resistance control 失效
标题翻译：双重SOI膜厚度用于体电阻控制
公开(公告)号：US07253068B1
公开(公告)日：2007-08-07
申请号：US10834095
申请日：2004-04-29
申请人： Dong-Hyuk Ju , Srinath Krishnan , Mario Pelella
发明人： Dong-Hyuk Ju , Srinath Krishnan , Mario Pelella
IPC分类号： H01L21/331
CPC分类号： H01L29/7841 , H01L21/76264 , H01L21/823481 , H01L21/84 , H01L27/1203
摘要： The silicon-on-insulator (SOI) arrangement provides dual SOI film thicknesses for body-resistance control and provides a bulk silicon substrate on which a buried oxide (BOX) layer is provided. The BOX layer has recesses formed therein and unrecessed portions. The silicon layer is formed on the BOX layer and closes the recesses and covers the unrecessed portions of the BOX layer. Shallow trench isolation regions define and isolate first silicon regions from second silicon regions that each include one of the recesses. Floating-body devices are formed within the first silicon regions, which exhibit a first thickness, and body-tied devices are formed within the second silicon regions that include the thicker silicon of the recesses.
摘要翻译：绝缘体上硅（SOI）布置提供用于体电阻控制的双重SOI膜厚度，并提供其上提供掩埋氧化物（BOX）层的体硅衬底。 BOX层具有形成在其中的凹部和未加工的部分。硅层形成在BOX层上，封闭凹槽并覆盖BOX层的未加工部分。浅沟槽隔离区域限定并隔离第一硅区域与第二硅区域，每个硅区域包括凹陷之一。浮动体装置形成在第一硅区域内，其呈现第一厚度，并且在第二硅区域内形成体系绑定的装置，该第二硅区域包括较厚的凹槽硅。

10. 发明授权

US06717212B2 Leaky, thermally conductive insulator material (LTCIM) in semiconductor-on-insulator (SOI) structure 有权
标题翻译：绝缘体上绝缘体（SOI）结构中的漏电导热绝缘体材料（LTCIM）
公开(公告)号：US06717212B2
公开(公告)日：2004-04-06
申请号：US09879724
申请日：2001-06-12
申请人： Dong-Hyuk Ju , William George En , Srinath Krishnan , Concetta E. Riccobene , Zoran Krivokapic , Judy Xilin An , Bin Yu
发明人： Dong-Hyuk Ju , William George En , Srinath Krishnan , Concetta E. Riccobene , Zoran Krivokapic , Judy Xilin An , Bin Yu
IPC分类号： H01L31392
CPC分类号： H01L21/76254 , H01L21/187 , H01L29/78603 , H01L29/78606 , H01L29/78609 , H01L29/78612
摘要： A device and method for making a semiconductor-on-insulator (SOI) structure having a leaky, thermally conductive material (LTCIM) layer disposed between a semiconductor substrate and a semiconductor layer.
摘要翻译：一种用于制造绝缘体半导体（SOI）结构的装置和方法，其具有设置在半导体衬底和半导体层之间的具有泄漏的导热材料（LTCIM）层。

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