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1. 发明申请

US20070045692A1 Nonvolatile memory devices and methods of manufacturing the same 失效
标题翻译：非易失存储器件及其制造方法
公开(公告)号：US20070045692A1
公开(公告)日：2007-03-01
申请号：US11511469
申请日：2006-08-29
申请人： Dong-Chul Kim , In-Gyu Baek , Young-Kwan Cha , Moon-Sook Lee , Sang-Jin Park
发明人： Dong-Chul Kim , In-Gyu Baek , Young-Kwan Cha , Moon-Sook Lee , Sang-Jin Park
IPC分类号： H01L29/94
CPC分类号： H01L45/04 , H01L27/2436 , H01L45/1233 , H01L45/1246 , H01L45/146 , H01L45/1633
摘要： Nonvolatile memory devices and methods of manufacturing the same are provided. The nonvolatile memory devices may include an oxide layer formed of a resistance conversion material, a lower electrode, a nano-wire layer formed of a transition metal on the lower electrode, and an upper electrode formed on the oxide layer. According to example embodiments, a reset current may be stabilized by unifying a current path on the oxide layer.
摘要翻译：提供了非易失性存储器件及其制造方法。非易失性存储器件可以包括由电阻转换材料，下电极，由下电极上的过渡金属形成的纳米线层和形成在氧化物层上的上电极形成的氧化物层。根据示例性实施例，可以通过统一氧化物层上的电流路径来稳定复位电流。

2. 发明授权

US07446333B2 Nonvolatile memory devices and methods of manufacturing the same 失效
标题翻译：非易失存储器件及其制造方法
公开(公告)号：US07446333B2
公开(公告)日：2008-11-04
申请号：US11511469
申请日：2006-08-29
申请人： Dong-Chul Kim , In-Gyu Baek , Young-Kwan Cha , Moon-Sook Lee , Sang-Jin Park
发明人： Dong-Chul Kim , In-Gyu Baek , Young-Kwan Cha , Moon-Sook Lee , Sang-Jin Park
IPC分类号： H01L29/04
CPC分类号： H01L45/04 , H01L27/2436 , H01L45/1233 , H01L45/1246 , H01L45/146 , H01L45/1633
摘要： Nonvolatile memory devices and methods of manufacturing the same are provided. The nonvolatile memory devices may include an oxide layer formed of a resistance conversion material, a lower electrode, a nano-wire layer formed of a transition metal on the lower electrode, and an upper electrode formed on the oxide layer. According to example embodiments, a reset current may be stabilized by unifying a current path on the oxide layer.
摘要翻译：提供了非易失性存储器件及其制造方法。非易失性存储器件可以包括由电阻转换材料，下电极，由下电极上的过渡金属形成的纳米线层和形成在氧化物层上的上电极形成的氧化物层。根据示例性实施例，可以通过统一氧化物层上的电流路径来稳定复位电流。

3. 发明申请

US20080142878A1 Charge trap memory device and a method of manufacturing the same 审中-公开
标题翻译：电荷陷阱记忆装置及其制造方法
公开(公告)号：US20080142878A1
公开(公告)日：2008-06-19
申请号：US11978577
申请日：2007-10-30
申请人： Sang-moo Choi , Young-Kwan Cha , Kwang-soo Seol , Sang-Jin Park , Sang-min Shin , Ju-hee Park
发明人： Sang-moo Choi , Young-Kwan Cha , Kwang-soo Seol , Sang-Jin Park , Sang-min Shin , Ju-hee Park
IPC分类号： H01L29/792 , H01L21/3205
CPC分类号： H01L29/513 , B82Y10/00 , H01L29/40114 , H01L29/785
摘要： Provided are a charge trap memory device and a method of manufacturing the same. The charge trap memory device may comprise a gate structure including a plurality of metal oxide nanodots discontinuously arranged as a charge trap site on a substrate.
摘要翻译：提供了一种电荷陷阱存储器件及其制造方法。电荷陷阱存储器件可以包括栅极结构，其包括不连续地布置在衬底上的电荷陷阱位置的多个金属氧化物纳米点。

4. 发明申请

US20080132020A1 Method of forming silicon nano crystals and method of manufacturing memory devices having the same 审中-公开
标题翻译：形成硅纳米晶体的方法及其制造方法
公开(公告)号：US20080132020A1
公开(公告)日：2008-06-05
申请号：US11812275
申请日：2007-06-18
申请人： Young-kwan Cha , Young-soo Park , Sang-Jin Park , Sang-min Shin , Hyuck Lim , Jung-hoon Shin
发明人： Young-kwan Cha , Young-soo Park , Sang-Jin Park , Sang-min Shin , Hyuck Lim , Jung-hoon Shin
IPC分类号： H01L21/336 , H01L21/36
CPC分类号： H01L29/42332 , B82Y10/00 , H01L21/02532 , H01L21/02595 , H01L21/02601 , H01L21/02667 , H01L29/40114
摘要： Provided are methods of forming nano crystals and method of manufacturing a memory device suing the same. In an example embodiment, a method of forming nano crystals may include forming an amorphous film on a substrate and converting the amorphous film into an oxide film having the nano crystals by annealing the amorphous film under oxidizing conditions under which part of the crystallized film is oxidized.
摘要翻译：提供形成纳米晶体的方法和制造其的存储器件的方法。在一个示例性实施例中，形成纳米晶体的方法可以包括在衬底上形成非晶膜，并且通过在氧化条件下退火非晶膜而将非晶膜转化为具有纳米晶体的氧化膜，在氧化条件下，部分结晶膜被氧化。

5. 发明申请

US20070090444A1 Nonvolatile memory device including nano dot and method of fabricating the same 审中-公开
标题翻译：包括纳米点的非易失性存储器件及其制造方法
公开(公告)号：US20070090444A1
公开(公告)日：2007-04-26
申请号：US11584543
申请日：2006-10-23
申请人： Sang-Jin Park , Myoung-Jae Lee , Young-Kwan Cha , Sun-Ae Seo , Kyung-Sang Cho , Kwang-Soo Seol
发明人： Sang-Jin Park , Myoung-Jae Lee , Young-Kwan Cha , Sun-Ae Seo , Kyung-Sang Cho , Kwang-Soo Seol
IPC分类号： H01L29/76 , H01L21/8238
CPC分类号： H01L27/101 , H01L27/1052 , H01L27/115 , H01L27/2436 , H01L45/04 , H01L45/1233 , H01L45/1246 , H01L45/146 , H01L45/1608
摘要： A nonvolatile memory device including a nano dot and a method of fabricating the same are provided. The nonvolatile memory device may include a lower electrode, an oxide layer on the lower electrode, a nano dot in the oxide layer and an upper electrode on the oxide layer. In example embodiments, the current paths inside the oxide layer may be unified, thereby stabilizing the reset current.
摘要翻译：提供了包括纳米点的非易失性存储器件及其制造方法。非易失性存储器件可以包括下电极，下电极上的氧化物层，氧化物层中的纳米点和氧化物层上的上电极。在示例性实施例中，氧化物层内的电流路径可以是统一的，从而稳定复位电流。

6. 发明授权

US07542346B2 Memory device and method for operating the same 失效
标题翻译：存储器件及其操作方法
公开(公告)号：US07542346B2
公开(公告)日：2009-06-02
申请号：US11704204
申请日：2007-02-09
申请人： Sang-Jin Park , Young-Soo Park , Sang-Min Shin , Young-Kwan Cha
发明人： Sang-Jin Park , Young-Soo Park , Sang-Min Shin , Young-Kwan Cha
IPC分类号： G11C16/04
CPC分类号： G11C16/0416 , B82Y10/00 , G11C2216/06 , H01L29/42332 , H01L29/7881
摘要： A memory device and method for operating the same are provided. The example method may be directed to a method of performing a memory operation on a memory device, and may include applying a negative voltage bias to the memory device during a programming operation of the memory device and applying a positive voltage bias to the memory device during an erasing operation of the memory device. The example memory device may include a substrate and a gate structure formed on the substrate, the gate structure exhibiting a faster flat band voltage shift under a negative voltage bias than under a positive voltage bias, the gate structure receiving a negative voltage bias during a programming of the memory device and receiving a positive voltage bias during an erasing operation of the memory device.
摘要翻译：提供了一种用于操作该存储器件的存储器件和方法。示例性方法可以针对在存储器件上执行存储器操作的方法，并且可以包括在存储器件的编程操作期间向存储器件施加负电压偏压，并且在存储器件期间向存储器件施加正电压偏压存储器件的擦除操作。示例性存储器件可以包括衬底和形成在衬底上的栅极结构，栅极结构在负电压偏压下比在正电压偏压下表现出更快的平带电压偏移，栅极结构在编程期间接收负电压偏置并且在存储器件的擦除操作期间接收正电压偏置。

7. 发明授权

US07998804B2 Nonvolatile memory device including nano dot and method of fabricating the same 有权
标题翻译：包括纳米点的非易失性存储器件及其制造方法
公开(公告)号：US07998804B2
公开(公告)日：2011-08-16
申请号：US12318097
申请日：2008-12-22
申请人： Sang-Jin Park , Myoung-Jae Lee , Young-Kwan Cha , Sun-Ae Seo , Kyung-Sang Cho , Kwang-Soo Seol
发明人： Sang-Jin Park , Myoung-Jae Lee , Young-Kwan Cha , Sun-Ae Seo , Kyung-Sang Cho , Kwang-Soo Seol
IPC分类号： H01L21/8238 , H01L21/02
CPC分类号： H01L27/101 , H01L27/1052 , H01L27/115 , H01L27/2436 , H01L45/04 , H01L45/1233 , H01L45/1246 , H01L45/146 , H01L45/1608
摘要： A nonvolatile memory device including a nano dot and a method of fabricating the same are provided. The nonvolatile memory device may include a lower electrode, an oxide layer on the lower electrode, a nano dot in the oxide layer and an upper electrode on the oxide layer. In example embodiments, the current paths inside the oxide layer may be unified, thereby stabilizing the reset current.
摘要翻译：提供了包括纳米点的非易失性存储器件及其制造方法。非易失性存储器件可以包括下电极，下电极上的氧化物层，氧化物层中的纳米点和氧化物层上的上电极。在示例性实施例中，氧化物层内的电流路径可以是统一的，从而稳定复位电流。

8. 发明申请

US20070187730A1 Memory devices having charge trap layers 审中-公开
标题翻译：具有电荷陷阱层的存储器件
公开(公告)号：US20070187730A1
公开(公告)日：2007-08-16
申请号：US11635047
申请日：2006-12-07
申请人： Sang-Jin Park , Young-kwan Cha , Young-soo Park , Jung-hyun Lee , Suk-ho Choi
发明人： Sang-Jin Park , Young-kwan Cha , Young-soo Park , Jung-hyun Lee , Suk-ho Choi
IPC分类号： H01L29/76
CPC分类号： H01L29/513 , H01L29/42332 , H01L29/7882 , H01L29/792
摘要： Example embodiments may provide memory devices having a charge trap layer which includes a hole trap and an electron trap. The memory device may generate a relatively large flat band voltage gap according to an applied bias voltage. Accordingly, a stable multilevel cell may be realized.
摘要翻译：示例性实施例可以提供具有电荷陷阱层的存储器件，其包括空穴阱和电子阱。存储器件可以根据所施加的偏置电压产生相对较大的平带电压间隙。因此，可以实现稳定的多电平单元。

9. 发明申请

US20070211533A1 Memory device and method for operating the same 失效
标题翻译：存储器件及其操作方法
公开(公告)号：US20070211533A1
公开(公告)日：2007-09-13
申请号：US11704204
申请日：2007-02-09
申请人： Sang-Jin Park , Young-Soo Park , Sang-Min Shin , Young-Kwan Cha
发明人： Sang-Jin Park , Young-Soo Park , Sang-Min Shin , Young-Kwan Cha
IPC分类号： G11C16/04 , G11C11/34
CPC分类号： G11C16/0416 , B82Y10/00 , G11C2216/06 , H01L29/42332 , H01L29/7881
摘要： A memory device and method for operating the same are provided. The example method may be directed to a method of performing a memory operation on a memory device, and may include applying a negative voltage bias to the memory device during a programming operation of the memory device and applying a positive voltage bias to the memory device during an erasing operation of the memory device. The example memory device may include a substrate and a gate structure formed on the substrate, the gate structure exhibiting a faster flat band voltage shift under a negative voltage bias than under a positive voltage bias, the gate structure receiving a negative voltage bias during a programming of the memory device and receiving a positive voltage bias during an erasing operation of the memory device.
摘要翻译：提供了一种用于操作该存储器件的存储器件和方法。示例性方法可以针对在存储器件上执行存储器操作的方法，并且可以包括在存储器件的编程操作期间向存储器件施加负电压偏压，并且在存储器件期间向存储器件施加正电压偏压存储器件的擦除操作。示例性存储器件可以包括衬底和形成在衬底上的栅极结构，栅极结构在负电压偏压下比在正电压偏压下表现出更快的平带电压偏移，栅极结构在编程期间接收负电压偏置并且在存储器件的擦除操作期间接收正电压偏置。

10. 外观设计

USD686152S1 Battery 有权
公开(公告)号：USD686152S1
公开(公告)日：2013-07-16
申请号：US29428745
申请日：2012-08-02
申请人： Jeong-Seop Lee , Myung-Sook Kwon , Sang-Jin Park , Nam Sunwoo
设计人： Jeong-Seop Lee , Myung-Sook Kwon , Sang-Jin Park , Nam Sunwoo

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