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1. 发明授权

US07982646B2 Method and apparatus for matched quantum accurate feedback DACs 有权
标题翻译：用于匹配量子精确反馈DAC的方法和装置
公开(公告)号：US07982646B2
公开(公告)日：2011-07-19
申请号：US12184204
申请日：2008-07-31
申请人： Quentin P. Herr , Aaron A. Pesetski , John X. Przybysz , Donald L. Miller
发明人： Quentin P. Herr , Aaron A. Pesetski , John X. Przybysz , Donald L. Miller
IPC分类号： H03M3/00
CPC分类号： H03M3/454 , H03M3/422 , H03M3/47
摘要： A second order superconductor delta-sigma analog-to-digital modulator having an input for receiving an analog signal, a first integrator coupled to the input, a second integrator cascaded with the first integrator, and a quantum comparator digitizing output from the second integrator reduces quantization noise by providing matched quantum accurate DACs in a feedback loop between output from the quantum comparator and input to the first integrator. The matched quantum accurate feedback DACs produce identically repeatable voltage pulses, may be configured for multi-bit output, may be time-interleaved to permit higher clocking rates, and may be employed in a balanced bipolar configuration to allow inductive input coupling. Bipolar feedback is balanced when gain of a first DAC exceeds gain of a matched, opposite polarity DAC by the amount of implicit feedback from the comparator into the second integrator.
摘要翻译：具有用于接收模拟信号的输入端的第二级超导体Δ-Σ模数转换器，耦合到输入端的第一积分器，与第一积分器级联的第二积分器和来自第二积分器的量子比较器数字化输出减小通过在量子比较器的输出和第一积分器的输出之间的反馈回路中提供匹配的量子精确DAC来进行量化噪声。匹配的量子精确反馈DAC产生相同可重复的电压脉冲，可以被配置用于多位输出，可以被时间交织以允许更高的时钟速率，并且可以采用平衡双极配置来允许电感输入耦合。当第一个DAC的增益超过匹配的相反极性DAC的增益时，双极反馈被平衡，这是由比较器到第二个积分器的隐含反馈量。

2. 发明授权

US5327130A Spur-free sigma-delta modulator and multiple flux quanta feedback generator 失效
标题翻译：无支路Σ-Δ调制器和多通量量子反馈发生器
公开(公告)号：US5327130A
公开(公告)日：1994-07-05
申请号：US103844
申请日：1993-08-09
申请人： Joonhee Kang , John X. Przybysz , Donald L. Miller
发明人： Joonhee Kang , John X. Przybysz , Donald L. Miller
IPC分类号： G01R13/34 , H03K5/24 , H03M3/02 , H03M3/00 , G01R19/00
CPC分类号： G01R13/34 , H03K5/24 , H03M3/376 , H03M3/43
摘要： A spur-free sigma delta modulator analog-to-digital converter for converting an analog input signal to a digital output signal is provided. A race Josephson junction is provided between the pulse generator and the integrating inductor. The race Josephson junction emits a voltage pulse in response to every sampling pulse. This voltage pulse kills any retained persisting current in the integrating inductor. By adding the race Josephson junction, nonlinearities in the converter are eliminated.A multiple flux quanta feedback generator for creating a multiple digital pulse feedback in response to an input signal is provided. A quantizer connected to the input inductor produces a pulse when the current produced by the input inductor exceeds a predetermined amount. A splitter is connected to the quantizer for producing output pulses. In order to produce 2.sup.n output pulses, 2.sup.n -1 splitters are required. Each of the splitters produces two output pulses in response to a single pulse produced by the quantizer. Each of the 2.sup.n output pulses drives one of 2.sup.n feedback pulse generators. Each of the feedback pulse generators is connected to one of the output pulses to produce 2.sup.n +1 quanta feedback which is fed back to the input inductor.
摘要翻译：提供了一种用于将模拟输入信号转换为数字输出信号的无差动Σ-Δ调制器模拟 - 数字转换器。在脉冲发生器和积分电感之间提供一个比赛约瑟夫逊结。比赛约瑟夫逊结响应于每个采样脉冲发出电压脉冲。该电压脉冲杀死积分电感器中的任何保留的持续电流。通过添加比赛约瑟夫逊结，消除了转换器中的非线性。提供了用于响应于输入信号产生多个数字脉冲反馈的多通量量子反馈发生器。当输入电感器产生的电流超过预定量时，连接到输入电感器的量化器产生脉冲。分路器连接到量化器以产生输出脉冲。为了产生2n个输出脉冲，需要2n-1个分离器。每个分离器响应于由量化器产生的单个脉冲产生两个输出脉冲。 2n个输出脉冲中的每一个驱动2n个反馈脉冲发生器中的一个。每个反馈脉冲发生器连接到一个输出脉冲以产生被反馈到输入电感器的2n + 1个量子反馈。

3. 发明授权

US5140324A Superconducting sigma-delta analog-to-digital converter 失效
标题翻译：超导Σ-Δ模数转换器
公开(公告)号：US5140324A
公开(公告)日：1992-08-18
申请号：US710856
申请日：1991-06-06
申请人： John X. Przybysz , Donald L. Miller , Eric H. Naviasky
发明人： John X. Przybysz , Donald L. Miller , Eric H. Naviasky
IPC分类号： H03M3/02
CPC分类号： H03M3/456 , H03M3/43
摘要： A superconducting sigma-delta analog-to-digital converter utilizes a superconducting inductor as the integrator and a Josephson junction connected in series between the inductor and ground as the quantizer. A SQUID generates sampling pulses at a selected GHz frequency which add to the inductor current flowing through the Josephson junction. When the combined current through the Josephson junction exceeds the critical current of the Josephson junction, a voltage pulse is generated which kicks back into the inductor to reduce the inductor current. The voltage across the Josephson junction is, therefore, a one bit digital representation of the analog signal. This one bit digital signal is converted to a multi-bit digital signal preferably by a decimator having superconducting circuits which reduce the frequency of the multi-bit digital signal to a frequency which can be further processed by semiconductor processors. Preferably, a weighting function is utilized in a conversion to improve accuracy.
摘要翻译：超导Σ-Δ模数转换器利用超导电感器作为积分器，并且将约瑟夫逊结串联连接在电感器和地之间作为量化器。 SQUID以选定的GHz频率产生采样脉冲，这增加了流过约瑟夫逊结的电感电流。当通过约瑟夫逊结的组合电流超过约瑟夫逊结的临界电流时，产生电压脉冲，其将回到电感器中以减小电感器电流。因此，约瑟夫逊结上的电压是模拟信号的一位数字表示。该一比特数字信号优选地被具有超导电路的抽取器转换成多位数字信号，该超导电路将多比特数字信号的频率降低到可由半导体处理器进一步处理的频率。优选地，在转换中利用加权函数来提高精度。

4. 发明申请

US20100026538A1 METHOD AND APPARATUS FOR MATCHED QUANTUM ACCURATE FEEDBACK DACS 有权
标题翻译：匹配量子精确反馈DAC的方法和装置
公开(公告)号：US20100026538A1
公开(公告)日：2010-02-04
申请号：US12184204
申请日：2008-07-31
申请人： Quentin P. Herr , Aaron A. Pesetski , John X. Przybysz , Donald L. Miller
发明人： Quentin P. Herr , Aaron A. Pesetski , John X. Przybysz , Donald L. Miller
IPC分类号： H03M3/02
CPC分类号： H03M3/454 , H03M3/422 , H03M3/47
摘要： A second order superconductor delta-sigma analog-to-digital modulator having an input for receiving an analog signal, a first integrator coupled to the input, a second integrator cascaded with the first integrator, and a quantum comparator digitizing output from the second integrator reduces quantization noise by providing matched quantum accurate DACs in a feedback loop between output from the quantum comparator and input to the first integrator. The matched quantum accurate feedback DACs produce identically repeatable voltage pulses, may be configured for multi-bit output, may be time-interleaved to permit higher clocking rates, and may be employed in a balanced bipolar configuration to allow inductive input coupling. Bipolar feedback is balanced when gain of a first DAC exceeds gain of a matched, opposite polarity DAC by the amount of implicit feedback from the comparator into the second integrator.
摘要翻译：具有用于接收模拟信号的输入端的第二级超导体Δ-Σ模数转换器，耦合到输入端的第一积分器，与第一积分器级联的第二积分器和来自第二积分器的量子比较器数字化输出减小通过在量子比较器的输出和第一积分器的输出之间的反馈回路中提供匹配的量子精确DAC来进行量化噪声。匹配的量子精确反馈DAC产生相同可重复的电压脉冲，可以被配置用于多位输出，可以被时间交织以允许更高的时钟速率，并且可以采用平衡双极配置来允许电感输入耦合。当第一个DAC的增益超过匹配的相反极性DAC的增益时，双极反馈被平衡，这是由比较器到第二个积分器的隐含反馈量。

5. 发明授权

US5341136A Bandpass sigma-delta modulator for analog-to-digital converters 失效
标题翻译：用于模数转换器的带通Σ-Δ调制器
公开(公告)号：US5341136A
公开(公告)日：1994-08-23
申请号：US945803
申请日：1992-09-16
申请人： John X. Przybysz , Donald L. Miller
发明人： John X. Przybysz , Donald L. Miller
IPC分类号： H03M3/02 , H03M1/00
CPC分类号： H03M3/404 , H03M3/43 , H03M3/456
摘要： A bandpass sigma-delta modulator for an analog-to-digital converter is provided in which an RLC circuit connected to the input analog signal is resonant at an intermediate frequency. A Josephson junction connected to the RLC circuit receives the current flowing through the RLC circuit. The Josephson junction emits a voltage pulse which reduces the RLC circuit current when the current in the Josephson junction exceeds its critical current. Selected multiples of the voltage pulse generated by the Josephson junction are fed back to the RLC circuit. A digital output is generated from the voltage pulses generated by the Josephson junction to complete the analog-to-digital conversion of the input signal.
摘要翻译：提供了一种用于模数转换器的带通Σ-Δ调制器，其中连接到输入模拟信号的RLC电路以中间频率谐振。连接到RLC电路的约瑟夫逊结接收流过RLC电路的电流。约瑟夫逊结发出电压脉冲，当约瑟夫逊结中的电流超过其临界电流时，该电压脉冲降低RLC电路电流。由约瑟夫逊结产生的电压脉冲的选定倍数反馈给RLC电路。从约瑟夫逊结产生的电压脉冲产生数字输出，以完成输入信号的模数转换。

6. 发明授权

US5289400A Single-flux-quantum multiply-accumulator 失效
标题翻译：单通量 - 量子倍增器
公开(公告)号：US5289400A
公开(公告)日：1994-02-22
申请号：US922251
申请日：1992-07-30
申请人： John X. Przybysz , Donald L. Miller , Joonhee Kang
发明人： John X. Przybysz , Donald L. Miller , Joonhee Kang
IPC分类号： G06F7/52
CPC分类号： G06F7/527
摘要： A serial multiplier for multiplying two n-bit numbers is provided in which a shift register having a total of n destructive read out cells contains a separate bit of a first multiplicand in each cell. A string of (2n-1) non-destructive read out cells is provided to receive the second multiplicand. Each of the first n cells of the string of non-destructive readout cells contain a separate bit of the second multiplicand. Each bit of the first multiplicand is serially multiplied with the series of bits of said second multiplicand. After each such multiplication, each bit of the second multiplicand is moved to the next adjacent cell. The partial product of the multiplication is stored in a string of 2n T flip-flop cells. Each of the T flip-flop cells has a carry path to the next adjacent T flip-flop cell. Timing means are provided to regulate and initiate the multiplication.
摘要翻译：提供了用于乘以两个n位数的串行乘法器，其中具有总共n个破坏性读出单元的移位寄存器在每个单元中包含第一被乘数的单独位。提供一串（2n-1）个非破坏性读出单元以接收第二被乘数。非破坏性读出单元串的前n个单元中的每一个包含第二被乘数的单独位。第一被乘数的每个比特与所述第二被乘数的一系列比特串联。在每次这样的乘法之后，第二被乘数的每个位被移动到下一个相邻的单元。乘法的部分乘积存储在2n T触发器单元的串中。每个T触发器单元具有到下一个相邻T触发器单元的进位路径。提供定时手段来调节和启动乘法。

7. 发明授权

US5198815A Two loop superconducting sigma-delta analog-to-digital converters 失效
标题翻译：双回路超导Σ-Δ模数转换器
公开(公告)号：US5198815A
公开(公告)日：1993-03-30
申请号：US807040
申请日：1991-12-12
申请人： John X. Przybysz , Donald L. Miller , Eric H. Naviasky
发明人： John X. Przybysz , Donald L. Miller , Eric H. Naviasky
IPC分类号： H03M3/02
CPC分类号： H03M3/438 , H03M3/43
摘要： A two-loop superconducting sigma-delta analog-to-digital converter includes a first superconducting inductor to which the analog signal is applied. A resistor converts to current in the first inductor to a voltage which is applied to a second superconducting inductor. The current in the second inductor, which increases quadradically with time, is applied to an overdamped Josephson junction which kicks back a single quantum voltage pulse each time its critical current is exceeded. This pulse reduces the current in the second inductor and serves as a digital ONE output. The pulses are also applied to an underdamped Josephson junction in a feedback pulse generator which latches at its gap voltage for the remainder of a half cycle of an ac bias current. This provides a voltage source for the primary of a superconducting transformer having a mutual inductance which produces sufficient flux in the secondary to cause a SQUID to generate in response to each pulse from the quantizer a selected number of feedback pulses which are applied to the first inductor.
摘要翻译：双回路超导Σ-Δ模数转换器包括施加模拟信号的第一超导电感器。电阻器将第一电感器中的电流转换为施加到第二超导电感器的电压。随着时间的推移，第二电感器中的电流逐渐增加，被施加到过阻尼的约瑟夫逊结，每当超过其临界电流时，它将踢回单个量子电压脉冲。该脉冲降低了第二电感器中的电流，并且用作数字ONE输出。脉冲也被施加到反馈脉冲发生器中的欠阻尼约瑟夫逊结，该反馈脉冲发生器在交流偏置电流的剩余半周期内以其间隙电压锁存。这为具有互感的超导变压器的初级电压提供电压源，该互感器在辅助电路中产生足够的通量，以使SQUID响应于来自量化器的每个脉冲而产生选定数量的反馈脉冲，该反馈脉冲施加到第一电感器。

8. 发明授权

US4536783A High di/dt, light-triggered thyristor with etched moat current limiting resistors 失效
标题翻译：高di / dt，光栅触发晶闸管，带蚀刻护环电流限制电阻
公开(公告)号：US4536783A
公开(公告)日：1985-08-20
申请号：US550849
申请日：1983-11-14
申请人： Donald L. Miller , John X. Przybysz
发明人： Donald L. Miller , John X. Przybysz
IPC分类号： H01L31/111 , H01L29/74
CPC分类号： H01L31/1113
摘要： The present invention is directed to a light-triggered thyristor having a high di/dt, high dv/dt, and high photosensitivity. The thyristor has a three-stage cathode emitter gating structure with integrated current limiting resistors. The current limiting resistors are defined by moats etched in the cathode base region. The moats also cause a "turn-on " current to flow through substantially all of the cathode base region.
摘要翻译：本发明涉及具有高di / dt，高dv / dt和高光敏性的光触发晶闸管。晶闸管具有集成限流电阻的三级阴极发射极门控结构。电流限制电阻由在阴极基极区域中蚀刻的护壁定义。护城河也导致“开启”电流流过基本上所有的阴极基极区域。

9. 发明申请

US20210063060A1 SOLID STATE COOLER DEVICE 有权
公开(公告)号：US20210063060A1
公开(公告)日：2021-03-04
申请号：US16554203
申请日：2019-08-28
申请人： Robert Miles Young , Aaron Ashley Hathaway , John X. Przybysz , Gregory R. Boyd , Zachary A. Stegen , Edward R. Engbrecht , Aaron A. Pesetski , Marc Eisenzweig Sherwin
发明人： Robert Miles Young , Aaron Ashley Hathaway , John X. Przybysz , Gregory R. Boyd , Zachary A. Stegen , Edward R. Engbrecht , Aaron A. Pesetski , Marc Eisenzweig Sherwin
IPC分类号： F25B21/00 , H01L39/06 , F25D31/00
摘要： A solid state cooler device is provided that includes a substrate, a first and second conductive pad disposed on the substrate, a first and second superconductor pad each having a side with a plurality of conductive pad contact interfaces spaced apart from one another and being in contact with a surface of respective first and second conductive pads, and a first and second insulating layer disposed between respective first and second superconductor pads, and respective ends of a normal metal layer. A bias voltage is applied between one of a first conductive pad or first superconductor pad and one of the second conductive pad or the second superconductor pad to remove hot electrons from the normal metal layer, and the contact area of the plurality of first and second conductive pad contact interfaces inhibits the transfer of heat back to the first and second superconductor pads.

10. 发明授权

US10229864B1 Cryogenic integrated circuit having a heat sink coupled to separate ground planes through differently sized thermal vias 有权
公开(公告)号：US10229864B1
公开(公告)日：2019-03-12
申请号：US15704919
申请日：2017-09-14
申请人： Patrick Loney , Robert Miles Young , Daniel Robert Queen , Aaron Ashley Hathaway , John X. Przybysz
发明人： Patrick Loney , Robert Miles Young , Daniel Robert Queen , Aaron Ashley Hathaway , John X. Przybysz
IPC分类号： H05K1/02 , H01L27/18 , H01L23/367 , H01L23/373 , H01L23/433
摘要： An integrated circuit is provided that comprises a thermal sink layer, a first ground plane associated with a first set of circuits that have a first operational temperature requirement, and a first thermally conductive via that couples the first ground plane to the thermal sink layer. The circuit further comprises a second ground plane associated with a second set of circuits that have a second operational temperature requirement that is higher than the first operational temperature requirement, and a second thermally conductive via that couples the second ground plane to the thermal sink layer, wherein the first thermally conductive via has a greater volume of thermal conductive material than the second thermally conductive via to remove heat from the first set of circuits with less gradient than the second set of circuits.

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