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1. 发明授权

US07498962B2 Analog-to-digital converter with low power track-and-hold mode 有权
标题翻译：具有低功率跟踪和保持模式的模数转换器
公开(公告)号：US07498962B2
公开(公告)日：2009-03-03
申请号：US11618644
申请日：2006-12-29
申请人： Donald E. Alfano , Danny J. Allred , Douglas S. Piasecki , Kenneth W. Fernald , Ka Y. Leung , Brian Caloway , Alvin Storvik , Paul Highley , Douglas R. Holberg
发明人： Donald E. Alfano , Danny J. Allred , Douglas S. Piasecki , Kenneth W. Fernald , Ka Y. Leung , Brian Caloway , Alvin Storvik , Paul Highley , Douglas R. Holberg
IPC分类号： H03M1/00
CPC分类号： G06F13/385 , G06F1/08 , G06F15/7814 , H03M1/122 , H03M1/183 , H03M1/462 , Y02D10/12 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： A method for converting analog data to digital data includes operating an analog-to-digital data converter in a tracking mode to sample an input signal and in a convert mode to convert the sampled input signal after sampling to a digital signal. The analog-to-digital data converter is controlled with a controller to operate in different modes of operation by providing at least one step wherein the tracking mode of operation is controlled to initiate at a predetermined time to begin the sampling operation.
摘要翻译：一种将模拟数据转换为数字数据的方法包括以跟踪模式操作模拟数字数据转换器，以对输入信号进行采样，并以转换模式将采样后的采样输入信号转换为数字信号。模拟数字数据转换器由控制器控制，以通过提供至少一个步骤操作在不同的操作模式，其中跟踪操作模式被控制以在预定时间开始以开始采样操作。

2. 发明授权

US07613901B2 Comparators in IC with programmably controlled positive / negative hysteresis level and open-drain / push-pull output coupled to crossbar switch or rising / falling edge interrupt generation 有权
标题翻译： IC中的比较器具有可编程控制的正/负滞后电平和开漏/推挽输出，连接到交叉开关或上升/下降沿中断产生
公开(公告)号：US07613901B2
公开(公告)日：2009-11-03
申请号：US11694629
申请日：2007-03-30
申请人： Donald E. Alfano , Danny J. Allred , Douglas S. Piasecki , Kenneth W. Fernald , Ka Y. Leung , Brian Caloway , Alvin Storvik , Paul Highley , Douglas R. Holberg
发明人： Donald E. Alfano , Danny J. Allred , Douglas S. Piasecki , Kenneth W. Fernald , Ka Y. Leung , Brian Caloway , Alvin Storvik , Paul Highley , Douglas R. Holberg
IPC分类号： G06F19/00 , H03K5/22
CPC分类号： G06F13/385 , G06F1/08 , G06F15/7814 , H03M1/122 , H03M1/183 , H03M1/462 , Y02D10/12 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： An integrated circuit package includes a processing core for operating on a set of instructions to carry out predefined processes. A plurality of comparators perform compare operations within the integrated circuit package. At least one control register is associated with each of the plurality of comparators, and each of the plurality of comparators are software programmable to control a hysteresis of the comparators responsive to control bits established in the at least one control register of the comparator by the processing core. An amount of positive hysteresis is programmed via a first group of the control bits and an amount of negative hysteresis is programmed via a second group of the control bits.
摘要翻译：集成电路封装包括用于对一组指令进行操作以执行预定义的处理的处理核心。多个比较器执行集成电路封装内的比较操作。至少一个控制寄存器与多个比较器中的每个比较器相关联，并且多个比较器中的每一个可软件编程以响应于通过处理在比较器的至少一个控制寄存器中建立的控制位来控制比较器的滞后核心。通过第一组控制位来编程正滞后量，经由第二组控制位来编程负滞后量。

3. 发明授权

US07504900B2 Integrated circuit package including programmable oscillators 有权
标题翻译：集成电路封装，包括可编程振荡器
公开(公告)号：US07504900B2
公开(公告)日：2009-03-17
申请号：US11694624
申请日：2007-03-30
申请人： Donald E. Alfano , Danny J. Allred , Douglas S. Piasecki , Kenneth W. Fernald , Ka Y. Leung , Brian Caloway , Alan Storvik , Paul Highley , Douglas R. Holberg
发明人： Donald E. Alfano , Danny J. Allred , Douglas S. Piasecki , Kenneth W. Fernald , Ka Y. Leung , Brian Caloway , Alan Storvik , Paul Highley , Douglas R. Holberg
IPC分类号： G06F1/04 , H03B5/00 , H03B5/12 , H03B5/24 , H03B5/36
CPC分类号： G06F13/385 , G06F1/08 , G06F15/7814 , H03M1/122 , H03M1/183 , H03M1/462 , Y02D10/12 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： An integrated circuit package includes a processing core and an internal oscillator. The processing core operates on a set of instructions to carry out predefined processes. The internal oscillator provides a system clock for the integrated circuit package. The internal oscillator has associated therewith an internal control register for controlling the operation of the internal oscillator responsive to control bits of the internal oscillator controlled by the processing core.
摘要翻译：集成电路封装包括处理核心和内部振荡器。处理核心通过一组指令来执行预定义的过程。内部振荡器为集成电路封装提供系统时钟。内部振荡器具有与其相关联的内部控制寄存器，用于响应于由处理核心控制的内部振荡器的控制位来控制内部振荡器的操作。

4. 发明授权

US07660968B2 Reconfigurable interface for coupling functional input/output blocks to limited number of I/O pins 有权
标题翻译：可重构接口，用于将功能输入/输出块耦合到有限数量的I / O引脚
公开(公告)号：US07660968B2
公开(公告)日：2010-02-09
申请号：US11772184
申请日：2007-06-30
申请人： Donald E. Alfano , Danny J. Allred , Douglas S. Piasecki , Kenneth W. Fernald , Ka Y. Leung , Brian Caloway , Alan Storvik , Paul Highley , Douglas R. Holberg
发明人： Donald E. Alfano , Danny J. Allred , Douglas S. Piasecki , Kenneth W. Fernald , Ka Y. Leung , Brian Caloway , Alan Storvik , Paul Highley , Douglas R. Holberg
IPC分类号： G06F13/00
CPC分类号： G06F13/385 , G06F1/08 , G06F15/7814 , H03M1/122 , H03M1/183 , H03M1/462 , Y02D10/12 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： A reconfigurable processor includes a processor core for operating on a set of instructions to carry out predefined processes and includes a plurality of input/output pins in addition to a plurality of functional input/output blocks. These functional blocks allow the processing core to interface with the plurality of input/output pins, each of the functional input/output blocks having an associated and predetermined functionality. This functionality comprises the output as a function of the input, the function defined by the functionality. Each of the functional input/output blocks has a requirement for a defined number of the plurality of input/output pins wherein the total of the defined number for all of the plurality of functional input/output blocks exceeds the number of the plurality of input/output pins and wherein the processor core is interfaced with one of the input or output of each of the functional blocks. A reconfigurable interface selectively interfaces between the other of the input or output of the functional blocks and a select one or ones of the plurality of input/output pins, such that the processor core can be interfaced with the select one or ones of the input/output pins. The reconfigurable interface is operable to define how each of the plurality of input/output pins interfaces with the select ones of the plurality of functional blocks and the associated functionality in accordance with configuration information. A non-volatile memory is provided for storing information for use in association with the configuration information, such that the stored information can be altered.
摘要翻译：可重构处理器包括用于在一组指令上操作以执行预定义的处理的处理器核心，并且除了多个功能输入/输出块之外还包括多个输入/输出引脚。这些功能块允许处理核与多个输入/输出引脚相连接，每个功能输入/输出块具有相关联的和预定的功能。该功能包括作为输入的功能的输出，功能定义的功能。每个功能输入/输出块对多个输入/输出引脚的定义数量要求，其中所有多个功能输入/输出块中的所有定义数目的总数超过多个输入/ 输出引脚，并且其中处理器核心与每个功能块的输入或输出中的一个接口。可重配置接口选择性地在功能块的输入或输出中的另一个与多个输入/输出引脚中的选择一个或多个输入/输出引脚之间进行接口，使得处理器核可以与选择的一个或多个输入/ 输出引脚。可重配置接口可操作以根据配置信息定义多个输入/输出引脚中的每一个如何与多个功能块中的选择功能块和相关联的功能接口。提供非易失性存储器用于存储与配置信息相关联使用的信息，使得可以改变所存储的信息。

5. 发明授权

US07171542B1 Reconfigurable interface for coupling functional input/output blocks to limited number of i/o pins 失效
标题翻译：用于将功能输入/输出块耦合到有限数量的I / O引脚的可重新配置的接口
公开(公告)号：US07171542B1
公开(公告)日：2007-01-30
申请号：US09885459
申请日：2001-06-19
申请人： Donald E. Alfano , Danny Allred , Douglas S. Piasecki , Kenneth W. Fernald , Ka Y Leung , Brian Caloway , Alvin Storvik , Paul Highley , Douglas R Holberg
发明人： Donald E. Alfano , Danny Allred , Douglas S. Piasecki , Kenneth W. Fernald , Ka Y Leung , Brian Caloway , Alvin Storvik , Paul Highley , Douglas R Holberg
IPC分类号： G06F13/00
CPC分类号： G06F13/385 , G06F1/08 , G06F15/7814 , H03M1/122 , H03M1/183 , H03M1/462 , Y02D10/12 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： A reconfigurable processor system n an intergrated circuit includes a processor core that operates on a set of instructions to carry out predefined processes. A plurality of input/output pins are provided for interfacing with external signals. A reconfigurable interface interfaces between the processor core and the input/output pins through select ones of a plurality of functional blocks. The reconfigurable interface is operable to define how each of the plurality of input/output pins interfaces with the processor core an the functionality associated therewith. The functional blocks provide the interface of the processor core with the input/output pins.
摘要翻译：集成电路中的可重构处理器系统包括对一组指令进行操作以执行预定义的处理的处理器核心。提供多个输入/输出引脚用于与外部信号进行接口。可重新配置的接口通过多个功能块中的选择的接口在处理器核心和输入/输出引脚之间进行接口。可重构接口可操作以定义多个输入/输出引脚中的每一个如何与处理器核心与处理器核心相连接的功能。功能块提供处理器内核与输入/输出引脚的接口。

6. 发明授权

US06456220B1 Analog-to-digital converter for processing differential and single-ended inputs 有权
标题翻译：用于处理差分和单端输入的模数转换器
公开(公告)号：US06456220B1
公开(公告)日：2002-09-24
申请号：US09595959
申请日：2000-06-19
申请人： Ka Y. Leung , Douglas S. Piasecki
发明人： Ka Y. Leung , Douglas S. Piasecki
IPC分类号： H03M112
CPC分类号： H03M1/129 , H03M1/46
摘要： An analog-to-digital converter configurable for converting both differential and single-ended analog signals. Charge sharing between two input capacitors and a DAC capacitor allow the full dynamic range of the ADC device to be used when full scale differential analog input signals are converted. When configured for single-ended operation, charge sharing of the half scale single-ended input analog voltage occurs between one input capacitor and the DAC capacitor to allow the full dynamic range of the ADC device to again be utilized.
摘要翻译：可配置用于转换差分和单端模拟信号的模数转换器。两个输入电容和DAC电容之间的电荷共享允许在转换满量程差分模拟输入信号时使用ADC器件的全部动态范围。当配置为单端操作时，半标准单端输入模拟电压的电荷共享发生在一个输入电容和DAC电容之间，以允许再次使用ADC器件的完整动态范围。

7. 发明授权

US06529152B1 High precision SAR converter using resistor strip with auto zeroing function 有权
标题翻译：高精度SAR转换器采用带自动调零功能的电阻条
公开(公告)号：US06529152B1
公开(公告)日：2003-03-04
申请号：US09901845
申请日：2001-07-09
申请人： Douglas S. Piasecki , Ka Y. Leung
发明人： Douglas S. Piasecki , Ka Y. Leung
IPC分类号： H03N166
CPC分类号： H03M1/682 , H03M1/46 , H03M1/765
摘要： A digital-to-analog converter having a semiconductor resistor strip with plural voltage taps. One voltage tap formed of the semiconductor material defines a nonzero reference voltage for the converter. An auto-zeroing amplifier is utilized to charge a coupling capacitor to the nonzero reference voltage. In the conversion process, the analog voltages at the other voltage taps of the resistor strip are selected via a switch arrangement and coupled to the coupling capacitor. The linearity of the digital-to-analog converter is thus more independent of parasitic resistances that may be formed in the ground connection to the resistor string.
摘要翻译：具有具有多个电压抽头的半导体电阻条的数 - 模转换器。由半导体材料形成的一个电压抽头为转换器定义非零参考电压。利用自动归零放大器将耦合电容器充电到非零参考电压。在转换过程中，电阻条的其他电压抽头上的模拟电压经由开关装置选择并耦合到耦合电容器。因此，数 - 模转换器的线性度与在与电阻串的接地连接中可能形成的寄生电阻更独立。

8. 发明授权

US06313779B1 Comparator-amplifier configuration in an ADC 有权
标题翻译： ADC中的比较器放大器配置
公开(公告)号：US06313779B1
公开(公告)日：2001-11-06
申请号：US09637493
申请日：2000-08-11
申请人： Ka Y. Leung , Douglas S. Piasecki
发明人： Ka Y. Leung , Douglas S. Piasecki
IPC分类号： H03M112
CPC分类号： H03M1/129 , H03M1/46
摘要： An analog-to-digital converter amplifier that is configurable with one gain for driving one terminal of a sampling capacitor while the other terminal is sampled to an analog input signal during one time period, and configurable with a different gain for comparing the analog sample with a DAC-generated reference voltage during a second time period.
摘要翻译：模数转换器放大器可配置一个增益，用于驱动采样电容器的一个端子，而另一个端子在一个时间段内被采样到模拟输入信号，并可配置不同的增益，用于将模拟采样与在第二时间段期间DAC产生的参考电压。

9. 发明授权

US06307497B1 Programmable gain ADC 有权
标题翻译：可编程增益ADC
公开(公告)号：US06307497B1
公开(公告)日：2001-10-23
申请号：US09638095
申请日：2000-08-11
申请人： Ka Y. Leung , Douglas S. Piasecki
发明人： Ka Y. Leung , Douglas S. Piasecki
IPC分类号： H03M116
CPC分类号： H03M1/129 , H03M1/46
摘要： A programmable gain circuit for analog-to-digital converter. A switched capacitor network capacitively couples an analog reference from a DAC to a comparator so that the sampled amplitude of the input analog signal can be compared with said analog reference. The ratio of the capacitance of the sampling capacitor to that of the switched capacitor network establishes an effective gain to the analog signal being converted.
摘要翻译：用于模数转换器的可编程增益电路。开关电容器网络将来自DAC的模拟基准电容耦合到比较器，使得可以将输入模拟信号的采样幅度与所述模拟参考值进行比较。采样电容器的电容与开关电容网络的电容之比建立了要转换的模拟信号的有效增益。

10. 发明授权

US07411538B1 SAR analog to digital converter having multiplexable ground sense pin 有权
标题翻译：具有可复用接地感测引脚的SAR模数转换器
公开(公告)号：US07411538B1
公开(公告)日：2008-08-12
申请号：US11695002
申请日：2007-03-31
申请人： Douglas S. Piasecki
发明人： Douglas S. Piasecki
IPC分类号： H03M1/38
CPC分类号： H03M1/0607 , H03M1/123 , H03M1/46 , H03M1/662 , H03M1/68 , H03M1/802
摘要： A circuit includes a successive approximation register A/D converter for performing analog to digital conversions. The register has a ground pin and a ground sense pin. The ground sense pin is connected to a ground port of the circuit. A multiplexer connects the ground sense pin of the successive approximation register A/D converter to one of a plurality of I/O ports of the circuit package. A switch selectively connects the ground sense pin of the successive approximation register A/D converter to the ground port.
摘要翻译：电路包括用于执行模数转换的逐次逼近寄存器A / D转换器。寄存器具有接地引脚和接地检测引脚。接地感测引脚连接到电路的接地端口。多路复用器将逐次逼近寄存器A / D转换器的接地检测引脚连接到电路封装的多个I / O端口之一。开关选择性地将逐次逼近寄存器A / D转换器的接地检测引脚连接到接地端口。

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