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    • 4. 发明授权
    • Chained operation of functional units in integrated circuit by writing DONE/complete value and by reading as GO/start value from same memory location
    • 通过写入DONE /完成值并通过从同一内存位置读取GO /起始值来对集成电路中的功能单元进行链接操作
    • US08156313B2
    • 2012-04-10
    • US12164089
    • 2008-06-29
    • Hirak MitraRaj KulkarniRichard WicksMichael Moon
    • Hirak MitraRaj KulkarniRichard WicksMichael Moon
    • G06F15/16
    • G06F15/7867Y02D10/12Y02D10/13
    • In an embodiment, the present invention discloses a flexible and reconfigurable architecture with efficient memory data management, together with efficient data transfer and relieving data transfer congestion in an integrated circuit. In an embodiment, the output of a first functional component is stored to an input memory of a next functional component. Thus when the first functional component completes its processing, its output is ready to be accessed as input to the next functional component. In an embodiment, the memory device further comprises a partition mechanism for simultaneously accepting output writing from the first functional component and accepting input reading from the second functional component. In another embodiment, the present integrated circuit comprises at least two functional components and at least two memory devices, together with a controller for switching the connections between the functional components and the memory devices. The controller can comprise a multiplexer or a switching matrix.
    • 在一个实施例中,本发明公开了一种具有高效存储器数据管理的灵活和可重新配置的架构,以及有效的数据传输和减轻集成电路中的数据传输拥塞。 在一个实施例中,第一功能组件的输出被存储到下一功能组件的输入存储器。 因此,当第一功能组件完成其处理时,其输出准备作为下一个功能组件的输入被访问。 在一个实施例中,存储器装置还包括分区机构,用于同时接收来自第一功能部件的输出写入并接收来自第二功能部件的输入读取。 在另一个实施例中,本集成电路包括至少两个功能组件和至少两个存储器设备,以及用于切换功能组件和存储设备之间的连接的控制器。 控制器可以包括多路复用器或开关矩阵。
    • 6. 发明申请
    • Soft-reconfigurable massively parallel architecture and programming system
    • 软件可重构的大容量并行架构和编程系统
    • US20090079466A1
    • 2009-03-26
    • US12164080
    • 2008-06-29
    • Hirak MitraRaj KulkarniRichard WicksMichael Moon
    • Hirak MitraRaj KulkarniRichard WicksMichael Moon
    • H03K19/173
    • G06F15/7867Y02D10/12Y02D10/13
    • The present disclosure provides an architecture that enables massive parallel processing on an IC while alleviating control congestion, memory access congestion and wiring congestion, together with high flexibility where the processing units are soft-arranged to perform different tasks. In an embodiment, the present architecture includes a functional block with a GO component to start the functional block, and a DONE component to identifying the completion status. The GO and DONE components can be linked together, preferably by a linkage component, to chain the functional blocks. The linkage is preferably soft configurable. In another embodiment, the present architecture includes an integrated circuit comprises a plurality of functional blocks chained together for serial processing, parallel processing, or any combination thereof.
    • 本公开提供了一种架构,其能够在缓解控制拥塞,存储器访问拥塞和布线拥塞的同时,在处理单元被软布置以执行不同任务的同时,实现对IC的大规模并行处理。 在一个实施例中,本架构包括具有用于启动功能块的GO组件的功能块和用于识别完成状态的DONE组件。 GO和DONE组件可以优选地通过连接组件链接在一起,以链接功能块。 该连杆优选是软配置的。 在另一个实施例中,本架构包括集成电路,其包括链接在一起用于串行处理,并行处理或其任何组合的多个功能块。
    • 7. 发明授权
    • Cable modem clock synchronization using software parsing with hardware assist
    • 电缆调制解调器时钟同步使用软件解析与硬件协助
    • US06744697B2
    • 2004-06-01
    • US09841022
    • 2001-04-24
    • Hirak MitraDavid Stark
    • Hirak MitraDavid Stark
    • G04C1300
    • H04N21/6168H04J3/0685H04N21/42676H04N21/4305H04N21/6118
    • SYNC parsing for Cable Modem Clock Synchronization is implemented using software processing with hardware assist in a manner that achieves the cost benefits of software SYNC parsing with the time accuracy of hardware SYNC parsing. Hardware scans for the arrival of new MPEG frames. Whenever any MPEG frame arrives, the MPEG frame is processed to extract MAC packets. If a SYNC packet is discovered during this processing, the software determines the SYNC arrival time, a comparison is made between the time the SYNC arrival time and the SYNC time value, and the software uses the difference to adjust the Cable Modem clock. Implementation variations include different approaches to when timestamps are recorded, the calculation of the SYNC arrival time, the use of software to process the MPEG frame and MAC packets, and the use of software to perform the time comparison.
    • 电缆调制解调器时钟同步的SYNC解析使用硬件辅助的软件处理实现,以实现硬件SYNC解析的时间精度来实现软件SYNC解析的成本优势。 硬件扫描新的MPEG帧的到来。 每当任何MPEG帧到达时,处理MPEG帧以提取MAC分组。 如果在此处理期间发现SYNC数据包,则软件确定SYNC到达时间,SYNC到达时间和SYNC时间值之间进行比较,软件使用差异来调整电缆调制解调器时钟。 执行变化包括记录时间戳,SYNC到达时间的计算,使用软件处理MPEG帧和MAC数据包以及使用软件执行时间比较的不同方法。