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1. 发明授权

US5617554A Physical address size selection and page size selection in an address translator 失效
标题翻译：地址翻译器中的物理地址大小选择和页面大小选择
公开(公告)号：US5617554A
公开(公告)日：1997-04-01
申请号：US372805
申请日：1994-12-23
申请人： Donald B. Alpert , Kenneth D. Shoemaker , Kevin C. Kahn , Konrad K. Lai
发明人： Donald B. Alpert , Kenneth D. Shoemaker , Kevin C. Kahn , Konrad K. Lai
IPC分类号： G06F12/10
CPC分类号： G06F12/1009 , G06F2212/652
摘要： An address translator and a method for translating a linear address into a physical address for memory management in a computer is described herein. Different memory sizes, and different page sizes can be selected. The address translator can translate from a standard 32-bit linear address for compatibility with previous 32-bit architectures, and can also translate to a physical memory size with a larger physical address than linear address; i.e., greater than 32 bits (e.g. 36 bits and up), with no increase in access time. The address translator translates a linear address that includes an offset and a plurality of fields used to select entries in a plurality of tables. The format of the linear address into fields is dependent upon the selected memory size and the selected page size. For a large memory size, the tables include a directory pointer table that includes a group of directory pointers, a plurality of page table directories each of which includes a group of page directory entries, and a plurality of page tables each of which includes a group of page table entries. The size of the entries in the tables is dependent upon the selected memory size. The contents of the tables are stored in memory, and furthermore the pointer table is stored in both main memory and in dedicated pointer table registers.
摘要翻译：这里描述了地址转换器和用于将线性地址翻译成用于计算机中的存储器管理的物理地址的方法。可以选择不同的内存大小和不同的页面大小。地址转换器可以从标准的32位线性地址转换，以兼容以前的32位体系结构，并且还可以转换为具有比线性地址更大的物理地址的物理内存大小; 即大于32位（例如36位及以上），而不增加访问时间。地址转换器翻译包括用于选择多个表中的条目的偏移和多个字段的线性地址。线性地址到字段的格式取决于所选的内存大小和所选的页面大小。对于大的存储器大小，表包括目录指针表，其包括一组目录指针，多个页表目录，每个页表目录包括一组页目录条目，以及多个页表，每个页表包括一组的页表条目。表中条目的大小取决于所选的内存大小。表的内容存储在存储器中，此外，指针表存储在主存储器和专用指针表寄存器中。

2. 发明授权

US5802605A Physical address size selection and page size selection in an address translator 失效
标题翻译：地址翻译器中的物理地址大小选择和页面大小选择
公开(公告)号：US5802605A
公开(公告)日：1998-09-01
申请号：US756184
申请日：1996-11-25
申请人： Donald B. Alpert , Kenneth D. Shoemaker , Kevin C. Kahn , Konrad K. Lai
发明人： Donald B. Alpert , Kenneth D. Shoemaker , Kevin C. Kahn , Konrad K. Lai
IPC分类号： G06F12/10
CPC分类号： G06F12/1009 , G06F2212/652
摘要： An address translator and a method for translating a linear address into a physical address for memory management in a computer is described herein. Different memory sizes, and different page sizes can be selected. The address translator can translate from a standard 32-bit linear address for compatibility with previous 32-bit architectures, and can also translate to a physical memory size with a larger physical address than linear address; i.e., greater than 32 bits (e.g. 36 bits and up), with no increase in access time. The address translator translates a linear address that includes an offset and a plurality of fields used to select entries in a plurality of tables. The format of the linear address into fields is dependent upon the selected memory size and the selected page size. For a large memory size, the tables include a directory pointer table that includes a group of directory pointers, a plurality of page table directories each of which includes a group of page directory entries, and a plurality of page tables each of which includes a group of page table entries. The size of the entries in the tables is dependent upon the selected memory size. The contents of the tables are stored in memory, and furthermore the pointer table is stored in both main memory and in dedicated pointer table registers.
摘要翻译：这里描述了地址转换器和用于将线性地址翻译成用于计算机中的存储器管理的物理地址的方法。可以选择不同的内存大小和不同的页面大小。地址转换器可以从标准的32位线性地址转换，以兼容以前的32位体系结构，并且还可以转换为具有比线性地址更大的物理地址的物理内存大小; 即大于32位（例如36位及以上），而不增加访问时间。地址转换器翻译包括用于选择多个表中的条目的偏移和多个字段的线性地址。线性地址到字段的格式取决于所选的内存大小和所选的页面大小。对于大的存储器大小，表包括目录指针表，其包括一组目录指针，多个页表目录，每个页表目录包括一组页目录条目，以及多个页表，每个页表包括一组的页表条目。表中条目的大小取决于所选的内存大小。表的内容存储在存储器中，此外，指针表存储在主存储器和专用指针表寄存器中。

3. 发明授权

US5638525A Processor capable of executing programs that contain RISC and CISC instructions 失效
标题翻译：处理器能够执行包含RISC和CISC指令的程序
公开(公告)号：US5638525A
公开(公告)日：1997-06-10
申请号：US386931
申请日：1995-02-10
申请人： Gary N. Hammond , Kevin C. Kahn , Donald B. Alpert
发明人： Gary N. Hammond , Kevin C. Kahn , Donald B. Alpert
IPC分类号： G06F9/30 , G06F9/318 , G06F9/38 , G06F9/455
CPC分类号： G06F9/3822 , G06F9/30043 , G06F9/30054 , G06F9/30076 , G06F9/30123 , G06F9/30174 , G06F9/30189 , G06F9/30196 , G06F9/45533
摘要： A data processor is described. The data processor is capable of decoding and executing the first instruction of a first instruction set and the second instruction of a second instruction set wherein the first instruction and the second instruction originate from a single computer program. Alternatively, the data processor can also execute a first instruction of a first instruction set in a first instruction set mode, receive a first interruption indication in the first instruction set mode, service the first interruption indication in a second instruction set mode, return to the first instruction set mode, receive a second interruption indication in the first instruction set mode, and service the second interruption indication in the first instruction set mode.
摘要翻译：描述数据处理器。数据处理器能够解码和执行第一指令集的第一指令和第二指令集的第二指令，其中第一指令和第二指令源于单个计算机程序。或者，数据处理器还可以以第一指令集模式执行第一指令集的第一指令，以第一指令集模式接收第一中断指示，以第二指令集模式服务第一中断指示，返回到第一指令集模式，以第一指令集模式接收第二中断指示，并在第一指令集模式下服务第二中断指示。

4. 发明授权

US06925083B2 Extending point-to-point/asynchronous transfer mode services to client computer systems 失效
标题翻译：将点对点/异步传输模式服务扩展到客户端计算机系统
公开(公告)号：US06925083B2
公开(公告)日：2005-08-02
申请号：US09949258
申请日：2001-09-07
申请人： Tsung-Yuan C. Tai , David B. Andersen , Charles L. Brabenac , Kevin C. Kahn
发明人： Tsung-Yuan C. Tai , David B. Andersen , Charles L. Brabenac , Kevin C. Kahn
IPC分类号： H04L12/28 , H04L12/56 , G06F15/16
CPC分类号： H04L12/2801
摘要： A method, apparatus, and system are provided for transmitting an Asynchronous Transfer Mode (ATM) cell from a server system to a broadband modem and forwarding the ATM cell from the broadband modem to a client system. According to one embodiment, a Broadband Modem Access Protocol (BMAP) unit is used to discover the identity of the broadband modem.
摘要翻译：提供了一种方法，装置和系统，用于将异步传输模式（ATM）小区从服务器系统传输到宽带调制解调器，并将ATM信元从宽带调制解调器转发到客户端系统。根据一个实施例，使用宽带调制解调器访问协议（BMAP）单元来发现宽带调制解调器的身份。

5. 发明授权

US4315310A Input/output data processing system 失效
标题翻译：输入/输出数据处理系统
公开(公告)号：US4315310A
公开(公告)日：1982-02-09
申请号：US79991
申请日：1979-09-28
申请人： John A. Bayliss , George W. Cox , Bert E. Forbes , Kevin C. Kahn
发明人： John A. Bayliss , George W. Cox , Bert E. Forbes , Kevin C. Kahn
IPC分类号： G06F12/02 , G06F13/12 , G06F13/42 , G06F15/16 , G06F15/177 , G06F3/00
CPC分类号： G06F12/0284 , G06F13/128 , G06F13/4208
摘要： An input/output processor architecture for providing an interface between peripheral subsystems and a generalized data processor. The interface processor enables data to be transferred between two address spaces (the generalized data processor address space and an external processor I/O address space) by mapping a portion of the I/O address space into a portion of the GDP address space. This mapping facility provides the peripheral subsystem with a "window" into the associated GDP subsystem. It accepts addresses within a certain subrange, or subranges, and translates them into references into one or more GDP data segments.A function-request facility provides a functional capability over certain objects within the GDP address space.The two facilities provide software on an external processor with a window into the address space of the GDP that enables the software, via the function request means, to send messages to and receive messages from the GDP and to manipulate an environment provided for the external processor within its address space.
摘要翻译：一种用于在外围子系统和广义数据处理器之间提供接口的输入/输出处理器架构。通过将I / O地址空间的一部分映射到GDP地址空间的一部分，接口处理器能够在两个地址空间（广义数据处理器地址空间和外部处理器I / O地址空间）之间传输数据。该映射设施为外围子系统提供了一个“窗口”到相关的GDP子系统中。它接受特定子范围内的地址或子范围，并将其转换为一个或多个GDP数据段的引用。功能请求功能可以在GDP地址空间内的某些对象上提供功能。这两个设施将外部处理器上的软件提供到GDP的地址空间中的窗口，使得软件能够通过功能请求装置向GDP发送消息并从其接收消息并且操纵为外部处理器提供的环境在其地址空间内。

6. 发明申请

US20130166813A1 MULTI-PROTOCOL I/O INTERCONNECT FLOW CONTROL 有权
标题翻译：多协议I / O互连流控制
公开(公告)号：US20130166813A1
公开(公告)日：2013-06-27
申请号：US13338230
申请日：2011-12-27
申请人： Prashant R. Chandra , Kevin C. Kahn
发明人： Prashant R. Chandra , Kevin C. Kahn
IPC分类号： G06F13/00
CPC分类号： G06F13/4022 , G06F13/385 , H04L45/52 , H04L47/39 , H04L49/505 , H04L49/602
摘要： Described are embodiments of methods, apparatuses, and systems for multi-protocol tunneling across a multi-protocol I/O interconnect of computer apparatus. A method for managing flow across the multi-protocol I/O interconnect may include providing, by a first port of a switching fabric of a multi-protocol interconnect to a second port of the switching fabric, a first credit grant packet and a second credit grant packet as indications of unoccupied space of a buffer associated with a path between the first port and a second port, and simultaneously routing a first data packet of a first protocol and a second data packet of a second protocol, different from the first protocol, on the path from the second port to the first port based at least in part on receipt by the second port of the first and second credit grant packets. Other embodiments may be described and claimed.
摘要翻译：描述了跨计算机设备的多协议I / O互连的多协议隧道传输的方法，装置和系统的实施例。用于管理跨多协议I / O互连的流的方法可以包括通过多协议互连的交换结构的第一端口向交换结构的第二端口提供第一授信分组和第二信用将分组作为与第一端口和第二端口之间的路径相关联的缓冲器的未占用空间的指示，并且同时路由与第一协议不同的第一协议的第一数据分组和第二协议的第二数据分组，至少部分地由第二端口接收到第一和第二信用授权分组在从第二端口到第一端口的路径上。可以描述和要求保护其他实施例。

7. 发明申请

US20130166798A1 MULTI-PROTOCOL TUNNELING OVER AN I/O INTERCONNECT 有权
标题翻译：多协议隧道在I / O互连上
公开(公告)号：US20130166798A1
公开(公告)日：2013-06-27
申请号：US13338227
申请日：2011-12-27
申请人： Prashant R. Chandra , Kevin C. Kahn , Eran Galil , Efraim Kugman , Naama Zolotov , Vladimir Yudovich , Yoni Dishon , Elli Bagelman
发明人： Prashant R. Chandra , Kevin C. Kahn , Eran Galil , Efraim Kugman , Naama Zolotov , Vladimir Yudovich , Yoni Dishon , Elli Bagelman
IPC分类号： G06F13/42
CPC分类号： G06F13/4022 , G06F13/4081
摘要： Described are embodiments of methods, apparatuses, and systems for multi-protocol tunneling across a multi-protocol I/O interconnect of computer apparatus. A method for multi-protocol tunneling may include establishing a first communication path between ports of a switching fabric of a multi-protocol interconnect of a computer apparatus in response to a peripheral device being connected to the computer apparatus, establishing a second communication path between the switching fabric and a protocol-specific controller, and routing, by the multi-protocol interconnect, packets of a protocol of the peripheral device from the peripheral device to the protocol-specific controller over the first and second communication paths. Other embodiments may be described and claimed.
摘要翻译：描述了跨计算机设备的多协议I / O互连的多协议隧道传输的方法，装置和系统的实施例。用于多协议隧道的方法可以包括响应于连接到计算机设备的外围设备在计算机设备的多协议互连的交换结构的端口之间建立第一通信路径，在第二通信路径之间建立第二通信路径交换结构和特定于协议的控制器，并且通过多协议互连，通过第一和第二通信路径将外围设备的协议的分组从外围设备路由到特定于协议的控制器。可以描述和要求保护其他实施例。

8. 发明申请

US20130163474A1 MULTI-PROTOCOL I/O INTERCONNECT ARCHITECTURE 有权
标题翻译：多协议I / O互连架构
公开(公告)号：US20130163474A1
公开(公告)日：2013-06-27
申请号：US13338222
申请日：2011-12-27
申请人： Prashant R. Chandra , Kevin C. Kahn
发明人： Prashant R. Chandra , Kevin C. Kahn
IPC分类号： H04L12/28
CPC分类号： H04L12/4625
摘要： Described are embodiments of methods, apparatuses, and systems for multi-protocol tunneling across a multi-protocol I/O interconnect of computer apparatus. A method for configuring a multi-protocol I/O interconnect may include identifying a plurality of switches of a switching fabric of a multi-protocol I/O interconnect, and configuring a path from a port of a first switch of the plurality of switches to a port of a second switch of the plurality of switches. Packets of a first protocol and packets of a second protocol, different from the first protocol, may be simultaneously routed over the path. Other embodiments may be described and claimed.
摘要翻译：描述了跨计算机设备的多协议I / O互连的多协议隧道传输的方法，装置和系统的实施例。用于配置多协议I / O互连的方法可以包括识别多协议I / O互连的交换结构的多个交换机，以及配置从多个交换机的第一交换机的端口到所述多个开关的第二开关的端口。不同于第一协议的第一协议的分组和第二协议的分组可以在路径上同时路由。可以描述和要求保护其他实施例。

9. 发明授权

US06795438B1 Method and apparatus for extending point-to-point/asynchronous transfer mode services to client computer systems 失效
标题翻译：将点对点/异步传输模式服务扩展到客户端计算机系统的方法和装置
公开(公告)号：US06795438B1
公开(公告)日：2004-09-21
申请号：US09182585
申请日：1998-10-28
申请人： Tsung-Yuan C. Tai , David B. Andersen , Charles L. Brabenac , Kevin C. Kahn
发明人： Tsung-Yuan C. Tai , David B. Andersen , Charles L. Brabenac , Kevin C. Kahn
IPC分类号： H04L1256
CPC分类号： H04L12/2801
摘要： A method for managing an asynchronous transfer mode (ATM) cell includes transmitting an ATM cell from a server system to a broadband modem. The ATM cell is forwarded from the broadband modem to a client system.
摘要翻译：一种用于管理异步传输模式（ATM）小区的方法包括将ATM信元从服务器系统发送到宽带调制解调器。 ATM信元从宽带调制解调器转发到客户端系统。

10. 发明授权

US5283904A Multi-processor programmable interrupt controller system 失效
标题翻译：多处理器可编程中断控制器系统
公开(公告)号：US5283904A
公开(公告)日：1994-02-01
申请号：US8074
申请日：1993-01-22
申请人： David G. Carson , Herman D. D'Hooge , Kevin C. Kahn
发明人： David G. Carson , Herman D. D'Hooge , Kevin C. Kahn
IPC分类号： G06F9/46 , G06F13/24 , G06F13/26 , G06F15/00 , G06F15/16 , G06F15/17 , G06F15/177
CPC分类号： G06F13/26 , G06F15/17
摘要： A multi-processor programmable interrupt controller system which includes: an I/O interrupt controller for receiving interrupt requests from an I/O subsystem; multiple processor interrupt controllers, each associated with a specific processor for dispensing of accepted interrupts; and an interrupt controller bus primarily for the transmission of interrupt requests between interrupt controller units and for priority arbitration, using a standard message format and arbitration protocol.
摘要翻译：一种多处理器可编程中断控制器系统，包括：I / O中断控制器，用于从I / O子系统接收中断请求; 多个处理器中断控制器，每个与特定处理器相关联，用于分配接受的中断; 以及主要用于在中断控制器单元之间传输中断请求并且使用标准消息格式和仲裁协议进行优先级仲裁的中断控制器总线。

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