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1. 发明授权

US06445685B1 Uplink demodulator scheme for a processing satellite 有权
标题翻译：用于处理卫星的上行链路解调器方案
公开(公告)号：US06445685B1
公开(公告)日：2002-09-03
申请号：US09407921
申请日：1999-09-29
申请人： Dominic P. Carrozza , Vincent C. Moretti , Stuart T. Linsky , David A. Wright , Gregory S. Caso
发明人： Dominic P. Carrozza , Vincent C. Moretti , Stuart T. Linsky , David A. Wright , Gregory S. Caso
IPC分类号： H04L27233
CPC分类号： H04L1/004 , H04B7/18515 , H04L27/22
摘要： An uplink demodulator system (44) for use in a processing satellite (12) in a satellite based communications system (10) is provided with a first multiplexer (62), a second multiplexer (82), a multichannel preamble processor (66), and a multichannel phase tracker (68). The first multiplexer (62) is operable to receive channelized data from a plurality of channelization modes at a plurality of inputs and operable to route the channelized data to a first output. The multichannel preamble processor (66) is operable to determine a phase estimate for each channel of the channelized data. The multichannel phase tracker (68) is operable to receive the phase estimates from the multichannel preamble processor (66) and operable to track a phase for each channel of said channelized data to phase align each channel of said channelized data to corresponding uplink signals. The second multiplexer (82) is operable to multiplex and route heavy encoded channelized data and light encoded channelized data to a second output where the multiplex channelized data is phase aligned with the corresponding uplink signals.
摘要翻译：一种在基于卫星的通信系统（10）中用于处理卫星（12）中的上行链路解调器系统（44）设置有第一多路复用器（62），第二多路复用器（82），多信道前同步码处理器（66）和多通道相位跟踪器（68）。第一多路复用器（62）可操作以在多个输入处从多个信道化模式接收信道化数据，并可操作以将信道化数据路由到第一输出。多信道前导码处理器（66）可操作以确定信道化数据的每个信道的相位估计。多通道相位跟踪器（68）可操作以从多通道前导码处理器（66）接收相位估计，并且可操作以跟踪所述信道化数据的每个信道的相位，以将所述信道化数据的每个信道相位对准相应的上行链路信号。第二多路复用器（82）可用于将重编码的信道化数据和光编码的信道化数据复用并路由到第二输出，其中多路信道化数据与对应的上行链路信号相位对准。

2. 发明授权

US06434361B1 Synchronization burst processor for a processing satellite 有权
标题翻译：用于处理卫星的同步突发处理器
公开(公告)号：US06434361B1
公开(公告)日：2002-08-13
申请号：US09408261
申请日：1999-09-29
申请人： Dominic P. Carrozza , Vincent C. Moretti , David A. Wright , Gregory S. Caso
发明人： Dominic P. Carrozza , Vincent C. Moretti , David A. Wright , Gregory S. Caso
IPC分类号： H04B7185
CPC分类号： H04L7/042 , H04B7/2125
摘要： A synchronization burst processor (56) used in a processing satellite (12) in a satellite based communications system (10) is provided with a sync burst memory (72), a first double correlator (74), a second double correlator (76) and a modulus module (78). The sync burst memory (72) stores at least one sync burst (52) transmitted from a terrestrial terminal (14) to the processing satellite (12) where the sync burst (52) is formed from a quadrature pair sample set {p, q}. The first double correlator (74) performs an early correlation and a late correlation of the p samples relative to a sync burst slot (50) to generate an early correlation Pe and a late correlation Pl. The second double correlator (76) performs an early correlation and a late correlation of the q samples relative to the sync burst slot (50) to generate an early correlation Qe and a late correlation Ql. The modulus module (78) determines an early modulus Re and a late modulus Rl from the early correlations Pe and Qe and from the late correlations Pl and Ql. The early modulus Re and the late modulus Rl are used to determine if the sync burst (52) is present in the sync burst slot (50) and if the sync burst (52) is early or late relative to the sync burst slot (50).
摘要翻译：在基于卫星的通信系统（10）中的处理卫星（12）中使用的同步突发处理器（56）具有同步脉冲串存储器（72），第一双相关器（74），第二双相关器（76）和模数模块（78）。同步突发存储器（72）存储从地面终端（14）发送到处理卫星（12）的至少一个同步脉冲串（52），其中同步脉冲串（52）由正交对采样集{p，q }。第一双相关器（74）执行相对于同步突发时隙（50）的p个样本的早期相关和后期相关，以产生早期相关Pe和晚期相关性P1。第二双相关器（76）执行相对于同步脉冲串时隙（50）的q个样本的早期相关和晚期相关，以产生早期相关Qe和晚期相关Q1。模量模块（78）从早期相关性Pe和Qe以及从晚期相关性P1和Q1确定早期模量Re和后期模量R1。早期模数Re和延迟模数R1用于确定同步脉冲串（52）是否存在于同步脉冲串时隙（50）中，并且如果同步脉冲串（52）相对于同步脉冲串时隙（50）早或晚）。

3. 发明授权

US06947500B1 Buffering and sequencing of soft decisions of multiple channels into a single shared biorthogonal decoder 有权
标题翻译：将多个信道的软判决缓冲和排序到单个共享双正交解码器中
公开(公告)号：US06947500B1
公开(公告)日：2005-09-20
申请号：US09239871
申请日：1999-01-29
申请人： Dominic P. Carrozza , Vincent C. Moretti , David A. Wright , Gregory S. Caso
发明人： Dominic P. Carrozza , Vincent C. Moretti , David A. Wright , Gregory S. Caso
IPC分类号： H03M13/37 , H03M13/45 , H04J3/00 , H04L1/00 , H04L27/22 , H04L27/06
CPC分类号： H04L1/0057 , H04L1/0052 , H04L1/0053 , H04L1/0065
摘要： The invention is a receiver and a method of receiving data having a preferred application in a satellite receiver in accordance with the invention includes a memory (114) including an addressable storage array which stores a sequence of data samples contained in a time division multiplexed signal from a plurality channels (X, Y and Z) and outputs the stored data samples in a sequence of data groups with each data group containing a plurality of samples from one of the plurality of channels; and a decoder (116), responsive to the data groups, which decodes the data samples within the data groups and outputs decoded data samples.
摘要翻译：本发明是一种在根据本发明的卫星接收机中接收具有优选应用的数据的接收机和方法，包括：存储器（114），包括可寻址存储阵列，其存储包含在时分多路复用信号中的数据样本序列，多个通道（X，Y和Z），并且从多个通道中的一个通道中的每个数据组包含多个采样的数据组序列中输出所存储的数据样本; 以及响应于数据组的解码器（116），其对数据组内的数据样本进行解码并输出解码的数据样本。

4. 发明授权

US06697344B1 Onboard initial entry processor for facilitating a satellite communication 失效
标题翻译：板载初始入口处理器，用于促进卫星通信
公开(公告)号：US06697344B1
公开(公告)日：2004-02-24
申请号：US09270167
申请日：1999-03-16
申请人： Dominic P. Carrozza , Gregory S. Caso , Vincent C. Moretti , Reginald Jue , David A. Wright
发明人： Dominic P. Carrozza , Gregory S. Caso , Vincent C. Moretti , Reginald Jue , David A. Wright
IPC分类号： H04B7185
CPC分类号： H04B7/1858
摘要： An initial entry processor (40) for use in a processing satellite (12) in a satellite based communications system (10) is provided having a buffer (62), a detection and timing circuit (64) and an identity circuit (66). The buffer (62) stores an initial entry burst (54) transmitted from at least one terrestrial terminal (14) to the processing satellite (12). The detection and timing circuit (64) detects the initial entry burst (54) and determines a time of arrival of the initial entry burst (54) relative to an initial entry burst slot (52). The identity circuit (66) determines an identity of the terrestrial terminal (14) that transmitted the initial entry burst (54) such that the time of arrival is used by the identified terrestrial terminal (14) during subsequent communications with the processing satellite (12).
摘要翻译：提供了一种用于基于卫星的通信系统（10）中的处理卫星（12）中的初始入口处理器（40），其具有缓冲器（62），检测和定时电路（64）以及标识电路（66）。缓冲器（62）存储从至少一个地面终端（14）发送到处理卫星（12）的初始入口突发（54）。检测和定时电路（64）检测初始入口突发（54）并且确定初始入口突发（54）相对于初始入口突发时隙（52）的到达时间。身份电路（66）确定发射初始入口突发（54）的地面终端（14）的身份，使得在与处理卫星（12）的后续通信期间由所识别的地面终端（14）使用到达时间）。

5. 发明授权

US06393066B1 Efficient digital channelizer system and method of operation thereof 有权
标题翻译：高效数字渠道化系统及其运行方法
公开(公告)号：US06393066B1
公开(公告)日：2002-05-21
申请号：US09259029
申请日：1999-02-26
申请人： Vincent C. Moretti , Dominic P. Carrozza , Gregory S. Caso
发明人： Vincent C. Moretti , Dominic P. Carrozza , Gregory S. Caso
IPC分类号： H04L2704
CPC分类号： H04J1/08 , H04L5/06
摘要： The invention is a digital channelizer and a process for dividing an input bandwidth into at least some of N channels. A digital channelizer which divides an input bandwidth into at least some of N channels in accordance with the invention includes an analog to digital converter (14); a demultiplexer (16), coupled to the analog to digital converter, a window presum (102) having N outputs, coupled to the parallel data streams, each output being a function of a window presum function and data words from a plurality of the parallel data streams; and a cyclic shift (24′), coupled to I output groups of data words.
摘要翻译：本发明是数字信道化器和将输入带宽划分成N个信道中的至少一些信道的过程。根据本发明的将输入带宽划分为N个信道中的至少一些的数字信道化器包括模数转换器（14）; 耦合到所述模数转换器的解复用器（16），具有N个输出的窗口（102），耦合到所述并行数据流，每个输出是窗口推定函数的函数，以及来自多个并行的数据字数据流以及耦合到I个输出数据字组的循环移位（24'）。

6. 发明授权

US06351759B1 Digital channelizer having efficient architecture for discrete fourier transformation and operation thereof 有权
标题翻译：数字信道化器具有用于离散傅里叶变换和其操作的有效架构
公开(公告)号：US06351759B1
公开(公告)日：2002-02-26
申请号：US09259623
申请日：1999-02-26
申请人： Vincent C. Moretti , Gregory S. Caso
发明人： Vincent C. Moretti , Gregory S. Caso
IPC分类号： G06F1714
CPC分类号： G06F17/141
摘要： The invention is an apparatus and process for performing a discrete Fourier transform and a digital channelizer which divides an input bandwidth into at least some of N channels. An apparatus for performing a discrete Fourier transform in accordance with the invention includes at least one discrete Fourier transform computation stage (304, 305′, 402, 410, 412, 414, 419), the at least one discrete Fourier transform computation stage having N inputs representing preselected frequency bands with each input containing an input signal containing real data and P actual outputs each containing an output signal, P being less than N, at least one of the P actual output signals containing a conjugate of one of the N input frequency bands; and a processing device (602, 702), coupled to at least one P actual output containing a signal which is a conjugate, which processes the conjugate as representative of one of the N input frequency bands.
摘要翻译：本发明是用于执行离散付里叶变换的装置和过程，以及将输入带宽分成至少一些N个信道的数字信道化器。根据本发明的用于执行离散付里叶变换的装置包括至少一个离散付里叶变换计算阶段（304,305'，402,410,412,414,419），所述至少一个离散付里叶变换计算阶段具有N 输入表示预选频带，每个输入包含包含实际数据的输入信号和每个包含P小于N的输出信号的P个实际输出，P个实际输出信号中的至少一个包含N个输入频率乐队以及耦合到包含作为共轭的信号的至少一个P实际输出的处理设备（602,702），其将所述共轭处理为代表N个输入频带之一。

7. 发明授权

US06349118B1 Digital channelizer having efficient architecture for cyclic shifting and method of operation thereof 有权
标题翻译：具有用于循环移位的有效结构的数字信道化及其操作方法
公开(公告)号：US06349118B1
公开(公告)日：2002-02-19
申请号：US09258847
申请日：1999-02-26
申请人： Gregory S. Caso , Vincent C. Moretti
发明人： Gregory S. Caso , Vincent C. Moretti
IPC分类号： H04L2704
CPC分类号： H04L5/06
摘要： The invention is a digital channelizer and a process for dividing an input bandwidth into at least some of N channels. A digital channelizer which divides an input bandwidth into at least some of N channels in accordance with the invention includes a window presum (102); a cyclic shift (24′), coupled to the I output groups of date words, having I cyclic shift paths, each cyclic shift path being responsive to a different output group of data words to produce I output groups of data words, each cyclic shift path comprising a plurality of word shifting elements each responsive to a group of data words; and a discrete Fourier transform (26′) coupled to the I output groups of cyclically shifted data words outputted from the cyclic shift.
摘要翻译：本发明是数字信道化器和将输入带宽划分成N个信道中的至少一些信道的过程。根据本发明，将输入带宽划分为至少一些N个信道的数字信道发送器包括窗口预测（102）; 耦合到具有I循环移位路径的I个输出组的日期字的循环移位（24'），每个循环移位路径响应不同的数据字输出组以产生I个数据字组，每个循环移位路径，其包括多个字移位元件，每个字移位元件响应于一组数据字; 以及耦合到从循环移位输出的循环移位数据字的I个输出组的离散傅里叶变换（26'）。

8. 发明授权

US06330287B1 Digital channelizer having efficient architecture for window presum using distributed arithmetic for providing window presum calculations in one clock cycle 有权
标题翻译：数字信道化器具有使用分布式算法的窗口高效架构，用于在一个时钟周期内提供窗口预测计算
公开(公告)号：US06330287B1
公开(公告)日：2001-12-11
申请号：US09259030
申请日：1999-02-26
申请人： Gregory S. Caso , Vincent C. Moretti
发明人： Gregory S. Caso , Vincent C. Moretti
IPC分类号： H04L2704
CPC分类号： G06F17/141
摘要： A digital channelizer and a process for dividing input bandwidth into at least some of N channels are disclosed. The digital channelizer which divides an input bandwidth into at least some of N channels in accordance with the invention includes an analog to digital converter (14), a demodulator (16) coupled to the analog to digital converter, a window presum (102) coupled to the parallel streams of data words and a discrete Fourier transform apparatus (26′), coupled to the N outputs of the window presum, having N inputs and which performs a discrete Fourier transform on the N inputs to output at least some of the N channels.
摘要翻译：公开了一种将输入带宽划分成N个信道中的至少一些的数字信道化器和处理。根据本发明，将输入带宽划分为N个信道中的至少一些的数字信道化器包括模数转换器（14），耦合到模数转换器的解调器（16），耦合到模拟数字转换器到数据字的并行流和离散傅立叶变换装置（26'），其耦合到具有N个输入的窗口的N个输出，并且在N个输入上执行离散傅里叶变换以输出N个输入中的至少一些频道

9. 发明授权

US07973645B1 RFID reader devices and methods thereof 有权
标题翻译： RFID读取器装置及其方法
公开(公告)号：US07973645B1
公开(公告)日：2011-07-05
申请号：US11807115
申请日：2007-05-25
申请人： Vincent C. Moretti , Mendy M. Ouzillou , Michael H. Thomas , Omer Onen , Ronald A. Oliver
发明人： Vincent C. Moretti , Mendy M. Ouzillou , Michael H. Thomas , Omer Onen , Ronald A. Oliver
IPC分类号： H04Q5/22
CPC分类号： G06K7/10356
摘要： Radio frequency identification (RFID) reader devices are disclosed. An RFID reader device of one aspect may include a radio frequency (RF) output port operable to allow a plurality of RFID antenna modules to be coupled with the RFID reader device. An RF signal generator of the device may be coupled with the RF output port. The RF signal generator may be operable to generate an RF signal and provide the RF signal to the RF output port. A select signal generator of the device may be operable to generate a select signal. The select signal may be operable to be output to select one or more of the plurality of RFID antenna modules.
摘要翻译：公开了射频识别（RFID）读取器装置。一个方面的RFID读取器装置可以包括可操作以允许多个RFID天线模块与RFID读取器装置耦合的射频（RF）输出端口。该装置的RF信号发生器可与RF输出端口耦合。 RF信号发生器可以用于产生RF信号并将RF信号提供给RF输出端口。设备的选择信号发生器可以用于产生选择信号。选择信号可以被操作以被输出以选择多个RFID天线模块中的一个或多个。

10. 发明授权

US08661652B1 RFID tag assembly methods 有权
标题翻译： RFID标签装配方法
公开(公告)号：US08661652B1
公开(公告)日：2014-03-04
申请号：US13456653
申请日：2012-04-26
申请人： Ronald L. Koepp , Ronald A. Oliver , William T. Colleran , Yanjun Ma , Jay M. Fassett , Vincent C. Moretti
发明人： Ronald L. Koepp , Ronald A. Oliver , William T. Colleran , Yanjun Ma , Jay M. Fassett , Vincent C. Moretti
IPC分类号： H01P11/00
CPC分类号： H01Q23/00 , G06K19/07756 , H01Q1/2208
摘要： RFID tags are assembled through affixing an antenna to an integrated circuit (IC) by forming one or more capacitors coupling the antenna and the IC with the dielectric material of the capacitor(s) including a non-conductive covering layer of the IC, a non-conductive covering layer of the antenna such as an oxide layer, and/or an additionally formed dielectric layer. Top and bottom plates of the capacitor(s) are formed by the antenna traces and one or more patches on a top surface of the IC.
摘要翻译： RFID标签通过将天线和IC的电容器与电容器的电介质材料形成一个或多个电容器组成，该电容器包括IC的非导电覆盖层，非集成电路天线的导电覆盖层，例如氧化物层，和/或另外形成的电介质层。电容器的顶板和底板由天线迹线和IC顶表面上的一个或多个贴片形成。

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