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    • 7. 发明授权
    • Logic chip, logic system and method for designing a logic chip
    • 逻辑芯片,逻辑系统和设计逻辑芯片的方法
    • US08018249B2
    • 2011-09-13
    • US12677474
    • 2008-09-08
    • Dirk KochThilo StreichertChristian HaubeltJuergen Teich
    • Dirk KochThilo StreichertChristian HaubeltJuergen Teich
    • G06F7/38H03K19/177
    • G06F15/7867G06F15/8015G06F17/5054H03K19/17736H03K19/17748H03K19/17796
    • A logic chip has a plurality of individually addressable resource blocks each of the resource blocks having logic circuitry, and a communication bar extending across a plurality of the individually addressable resource blocks. The communication bar has a plurality of communication bar segments associated with the resource slots. The communication bar segments of the individually addressable resource blocks have identical interface locations with respect to boundaries of the resource blocks, such that an input interface location of a first resource block matches an output interface location of an adjacent second resource block. At least one of the individually addressable resource blocks has a bypass segment of the communication bar. At least one of the individually addressable resource blocks has an access segment of the communication bar. The access segment has an access structure inserted between a first communication bar interface location and a second communication bar interface location, to allow for a read access or a write access or a combined read/write access to the communication bar.
    • 逻辑芯片具有多个可单独寻址的资源块,每个资源块具有逻辑电路,以及通过多个可单独寻址的资源块延伸的通信条。 通信条具有与资源槽相关联的多个通信条段。 可单独寻址的资源块的通信条段相对于资源块的边界具有相同的接口位置,使得第一资源块的输入接口位置与相邻的第二资源块的输出接口位置匹配。 至少一个可单独寻址的资源块具有通信条的旁路段。 可单独寻址的资源块中的至少一个具有通信条的访问段。 访问段具有插入在第一通信条接口位置和第二通信条接口位置之间的访问结构,以允许对通信条的读取访问或写入访问或组合的读/写访问。