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1. 发明授权

US07421007B2 Transmission/reception digital circuit in CDMA system 有权
标题翻译： CDMA系统中的发送/接收数字电路
公开(公告)号：US07421007B2
公开(公告)日：2008-09-02
申请号：US10450815
申请日：2001-12-27
申请人： Didier Lattard , Jean-Rene Lequepeys , Didier Varreau , Laurent Ouvry
发明人： Didier Lattard , Jean-Rene Lequepeys , Didier Varreau , Laurent Ouvry
IPC分类号： H04B1/69 , H04B7/216
CPC分类号： H04B1/7075 , H04B1/707 , H04W52/04
摘要： The present invention relates to a digital transmitting/receiving circuit (1) intended to be mounted on at least one source and on at least one concentrator exchanging binary symbols with the said sources, the said circuit (1) comprising a transmitter (2) capable of transmitting the said binary symbols and a receiver (4) capable of receiving symbols transmitted by a source, the circuit (1) being characterized in that the transmitter (2) comprises a first module (20) intended to generate at least one binary code for effecting the spectral spreading of symbols to be transmitted and a second module (22) intended to generate at least one internal clock signal for synchronizing the reception of symbols transmitted by a source, and in that the said receiver comprises means (46, 48) for detecting new sources of transmission and means (49) for generating synchronization signals and power control signals corresponding to each new source detected.
摘要翻译：本发明涉及一种旨在安装在至少一个源上的数字发射/接收电路（1）和至少一个与所述源交换二进制符号的集中器，所述电路（1）包括能够发送所述二进制符号和能够接收由源发送的符号的接收机（4），所述电路（1）的特征在于，所述发射机（2）包括第一模块（20），用于生成至少一个二进制码用于实现待传输的符号的频谱扩展;以及第二模块（22），其旨在产生用于同步由源发送的符号的接收的至少一个内部时钟信号，并且所述接收机包括装置（46,48）用于检测新的传输源和用于产生与检测到的每个新源相对应的同步信号和功率控制信号的装置（49）。

2. 发明申请

US20060078043A1 Receiver for a CDMA system 有权
标题翻译： CDMA系统接收机
公开(公告)号：US20060078043A1
公开(公告)日：2006-04-13
申请号：US11288663
申请日：2005-11-28
申请人： Laurent Ouvry , Didier Lattard , Jean-Rene Lequepeys
发明人： Laurent Ouvry , Didier Lattard , Jean-Rene Lequepeys
IPC分类号： H04B1/707
CPC分类号： H04B1/708 , H04B1/7095 , H04B2201/70707 , H04J13/0022
摘要： The receiver includes at least one channel (V1) with an adapted filter (20) and with a symbol clock signal (Hs) recovery circuit (12) and other channels (V2, . . . , Vk) with a sliding correlator (302, . . . , 30k) using the symbol clock signal (Hs) produced by the channel (V1) with adapted filter. Application for radiocommunications with mobiles.
摘要翻译：接收机包括具有适配滤波器（20）和符号时钟信号（Hs）恢复电路（12）和其它信道（V 2）的至少一个信道（V SUB 1）使用符号时钟的滑动相关器（30×2×...，30K），使用符号时钟由具有适配滤波器的通道（V SUB1）产生的信号（Hs）。移动电话无线电通信应用。

3. 再颁专利

USRE40716E1 CDMA receiver with parallel interference suppression and optimized synchronization 有权
标题翻译： CDMA接收机具有并行干扰抑制和优化同步
公开(公告)号：USRE40716E1
公开(公告)日：2009-06-02
申请号：US11593123
申请日：2006-11-02
申请人： Laurent Ouvry , Didier Varreau , Didier Lattard , Sebastien Leveque
发明人： Laurent Ouvry , Didier Varreau , Didier Lattard , Sebastien Leveque
IPC分类号： H04B1/00
CPC分类号： H04B1/71075 , H04B1/7093 , H04B1/7095
摘要： A receiver for transmission and parallel interference has multiple access interference suppression stages having K channels, each comprising a correlation device corresponding to a particular pseudorandom sequence and interference generation and suppression device. Each stage delivers to the following stage signals at least partly freed from multiple access interferences. A decision stage receives the signals from the channels of the preceding suppression stage. Each decision stage has a correlation device corresponding to one of the pseudorandom sequences and decision device to deliver data. Devices for producing synchronization signals can control the interference suppression and the decision device. The devices producing the synchronization signals have components placed in the channels of the final stage. Further, the synchronization signals produced by these devices control the decision device of the channels of the final stage and the interference estimation device of the at least one interference suppression stages following appropriate time shifts.
摘要翻译：用于传输和并行干扰的接收机具有具有K个信道的多个接入干扰抑制级，每个信道包括对应于特定伪随机序列和干扰产生和抑制装置的相关装置。每个阶段至少部分地从多个接入干扰中释放出下一个阶段的信号。判定级从前述抑制级的通道接收信号。每个决策阶段具有对应于伪随机序列和决策装置之一的相关装置以递送数据。用于产生同步信号的装置可以控制干扰抑制和决策装置。产生同步信号的装置具有放置在最后级的通道中的部件。此外，由这些装置产生的同步信号在适当的时移之后控制最后级的信道的判定装置和至少一个干扰抑制阶段的干扰估计装置。

4. 发明授权

US06813308B1 CDMA receiver with parallel interference suppression and optimized synchronization 有权
标题翻译： CDMA接收机具有并行干扰抑制和优化同步
公开(公告)号：US06813308B1
公开(公告)日：2004-11-02
申请号：US09598372
申请日：2000-06-21
申请人： Laurent Ouvry , Didier Varreau , Didier Lattard , Sébastien Leveque
发明人： Laurent Ouvry , Didier Varreau , Didier Lattard , Sébastien Leveque
IPC分类号： H04B1707
CPC分类号： H04B1/71075 , H04B1/7093 , H04B1/7095
摘要： A receiver for transmission and parallel interference has multiple access interference suppression stages having K channels, each comprising a correlation device corresponding to a particular pseudorandom sequence and interference generation and suppression device. Each stage delivers to the following stage signals at least partly freed from multiple access interferences. A decision stage receives the signals from the channels of the preceding suppression stage. Each decision stage has a correlation device corresponding to one of the pseudorandom sequences and decision device to deliver data. Devices for producing synchronization signals can control the interference suppression and the decision device. The devices producing the synchronization signals have components placed in the channels of the final stage. Further ,the synchronization signals produced by these devices control the decision device of the channels of the final stage and the interference estimation device of the at least one interference suppression stages following appropriate time shifts.
摘要翻译：用于传输和并行干扰的接收机具有具有K个信道的多个接入干扰抑制级，每个信道包括对应于特定伪随机序列和干扰产生和抑制装置的相关装置。每个阶段至少部分地从多个接入干扰中释放出下一个阶段的信号。判定级从前述抑制级的通道接收信号。每个决策阶段具有对应于伪随机序列和决策装置之一的相关装置以递送数据。用于产生同步信号的装置可以控制干扰抑制和决策装置。产生同步信号的装置具有放置在最后级的通道中的部件。此外，由这些装置产生的同步信号在适当的时移之后控制最后级的信道的判定装置和至少一个干扰抑制阶段的干扰估计装置。

5. 发明授权

US06115413A Process for the transmission of information by pulse response and the corresponding receiver 失效
标题翻译：通过脉冲响应传输信息的过程和相应的接收器
公开(公告)号：US06115413A
公开(公告)日：2000-09-05
申请号：US975459
申请日：1997-11-21
申请人： Didier Lattard , Jean-Rene Lequepeys , Norbert Daniele , Bernard Piaget
发明人： Didier Lattard , Jean-Rene Lequepeys , Norbert Daniele , Bernard Piaget
IPC分类号： H04B7/005 , H04B15/00 , H04K1/00 , H04L27/30
CPC分类号： H04B7/005
摘要： A differential receiver which receives a signal corresponding to transmission of a carrier modulated by symbols S.sub.k, where k is an integer designating an order of the symbol, each symbol S.sub.k has a duration Ts and carries information, and the symbols S.sub.k have been multiplied by a psuedorandom sequence. The differential receiver includes a first processing channel configured to receive a first part of the transmitted signal in phase with the carrier to generate samples I.sub.k and delayed samples I.sub.k-1. The receiver further includes a second processing channel configured to receive a second part of the transmitted signal in phase quadrature with the carrier to generate samples Q.sub.k and delayed samples Q.sub.k-1. In addition, the receiver includes a multiplication circuit configured to generate a signal Dot(k) equal to I.sub.k I.sub.k-1 +Q.sub.k Q.sub.k-1 and a signal Cross(k) equal to Q.sub.k I.sub.k-1 -I.sub.k Q.sub.k-1, a calculating mechanism configured to calculate, for each order k of a symbol, the following equation: E=[Dot(k).sup.2 +Cross(k).sup.2 ].sup.1/2, and configured to calculate a mean E.sup.moy, a weighting circuit having two multipliers configured to respectively multiply the signal E.sup.moy and the signals Dot(k) and Cross(k) to obtain a mean signal Dot(k).sup.moy and a mean signal Cross(k).sup.moy, and a circuit configured to receive the mean signal Dot(k).sup.moy and the mean signal Cross(k).sup.moy supplied by the calculating mechanism to integrate the mean signals on the time of a symbol and restore the corresponding information.
摘要翻译：接收对应于由符号Sk调制的载波的传输的信号的差分接收机，其中k是指定符号顺序的整数，每个符号Sk具有持续时间Ts并携带信息，并且符号Sk已经被乘以伪装序列。差分接收机包括第一处理通道，其被配置为接收与载波同相的发射信号的第一部分以产生采样Ik和延迟采样Ik-1。接收机还包括第二处理通道，其被配置为接收与载波相位正交的发射信号的第二部分以产生采样Q k和延迟采样Q k-1。此外，接收机包括：乘法电路，被配置为生成等于IkIk-1 + QkQk-1的信号Dot（k）和等于QkIk-1-IkQk-1的信号Cross（k），被配置为计算对于符号的每个阶数k，下列等式：E = [Dot（k）2 + Cross（k）2] + E，fra 1/2 + EE，并且被配置为计算平均值Emoy，加权电路具有两个乘法器，被配置为分别乘以信号Emoy和信号Dot（k）和Cross（k）以获得平均信号Dot（k）moy和平均信号Cross（k）moy，以及被配置为接收平均信号 Dot（k）moy和由计算机构提供的平均信号Cross（k）moy，以在符号时间上整合平均信号并恢复相应的信息。

6. 发明授权

US5799035A Digital circuit for differential receiver for direct sequence spread spectrum signals 失效
标题翻译：用于直接序列扩频信号的差分接收机的数字电路
公开(公告)号：US5799035A
公开(公告)日：1998-08-25
申请号：US747262
申请日：1996-11-12
申请人： Didier Lattard , Jean Rene Lequepeys , Bernard Piaget , Norbert Daniele
发明人： Didier Lattard , Jean Rene Lequepeys , Bernard Piaget , Norbert Daniele
IPC分类号： H04B1/707 , H04J13/00 , H04K1/00
CPC分类号： H04B1/7093
摘要： The circuit has two parallel channels for the processing of two components in phase (I) and in quadrature (Q). Each channel has filtering means (50(I)) and delay means (60(I)). The circuit also incorporates a multiplication circuit (70), an integration circuit (80) and a programming circuit (90). Several circuits of this type can be connected in cascade.
摘要翻译：该电路具有两个并行通道，用于处理相位（I）和正交（Q）中的两个分量。每个通道具有滤波装置（50（I））和延迟装置（60（I））。电路还包括乘法电路（70），积分电路（80）和编程电路（90）。这种类型的几个电路可以级联连接。

7. 发明授权

US06748007B1 Method of processing a pulse response with an adaptive threshold and corresponding receiver 失效
标题翻译：用自适应阈值处理脉冲响应的方法和对应的接收器
公开(公告)号：US06748007B1
公开(公告)日：2004-06-08
申请号：US09583746
申请日：2000-05-31
申请人： Didier Lattard , Jean-René Lequepeys , Didier Varreau , Mathieu Bouvier des Noes
发明人： Didier Lattard , Jean-René Lequepeys , Didier Varreau , Mathieu Bouvier des Noes
IPC分类号： H04L2730
CPC分类号： H04B1/707 , H04B1/7097
摘要： A method of processing a pulse response with an adaptive threshold and corresponding receiver. According to the method, an adaptive threshold is calculated that is a function of a maximum reached by the pulse response, noise, and a coefficient adjustable between 0 and 1. The processing only comes into operation for signals that exceed this threshold. Such a method may find application notably to digital radio-communications with spread spectrum.
摘要翻译：一种用自适应阈值和对应的接收器处理脉冲响应的方法。根据该方法，计算出由脉冲响应，噪声和0和1之间可调的系数达到的最大值的函数的自适应阈值。对于超过该阈值的信号，该处理仅对于操作。这种方法可以显着地应用于具有扩展频谱的数字无线电通信。

8. 发明授权

US06347112B1 Circuit for direct sequence spread spectrum digital transmissions with generation of an interference signal 有权
标题翻译：用于产生干扰信号的直接序列扩频数字传输电路
公开(公告)号：US06347112B1
公开(公告)日：2002-02-12
申请号：US09166544
申请日：1998-10-05
申请人： Didier Lattard , Jean-René Lequepeys , Didier Varreau , Bernard Piaget
发明人： Didier Lattard , Jean-René Lequepeys , Didier Varreau , Bernard Piaget
IPC分类号： H04B1500
CPC分类号： H04B1/7107
摘要： A circuit able to operate either as a direct sequence spread spectrum differential signal emitter, or as a generator of interference signals corresponding to multiple access noise. The circuit employs a clock signal formation and data processing module, a differential coding module, a multiplexing module, and a direct sequence spread module when operating as a spread spectrum emitter, and has an additional amplification-inversion module for use when generating an interference signal.
摘要翻译：一种能够作为直接序列扩频差分信号发射器工作的电路，或作为对应于多路存取噪声的干扰信号的发生器。当作为扩频发射器工作时，电路采用时钟信号形成和数据处理模块，差分编码模块，复用模块和直接序列扩展模块，并且具有用于当产生干扰信号时使用的附加放大反演模块。

9. 发明授权

US07391806B2 Digital data exchange device in a CDMA system 有权
标题翻译： CDMA系统中的数字数据交换设备
公开(公告)号：US07391806B2
公开(公告)日：2008-06-24
申请号：US10450447
申请日：2001-12-27
申请人： Didier Lattard , Didier Varreau , Bernard Piaget , Marc Laugeois
发明人： Didier Lattard , Didier Varreau , Bernard Piaget , Marc Laugeois
IPC分类号： H04L5/16
CPC分类号： H04B1/707 , H04B1/7075 , H04J13/004
摘要： The invention relates to a device for exchanging digital data between several sources and at least one hub in a CDMA system, characterized in that it comprises a number n of digital transmission/reception circuits (1) installed in parallel, each circuit (1) comprising a transmitter (2i) comprising means of generating an integer number Nc of codes that will be used for spectral spreading of data to be transmitted and a receiver (4i) comprising means (46, 48) of detecting the access of new sources to the CDMA system transmission channel and means (49) of generating synchronization signals and power control signals corresponding to each detected new source.
摘要翻译：本发明涉及一种用于在CDMA系统中的数个源和至少一个集线器之间交换数字数据的装置，其特征在于，它包括数个并行安装的数字发送/接收电路（1），每个电路（1）包括包括用于生成将用于要发送的数据的频谱扩展的代码的整数N N个代码的装置的发送器（2＆lt; i＆gt; i）和接收器（4

10. 发明授权

US06349109B1 Direct sequence spread spectrum differential receiver with mixed interference signal formation means 失效
标题翻译：具有混合干扰信号形成手段的直接序列扩频差分接收机
公开(公告)号：US06349109B1
公开(公告)日：2002-02-19
申请号：US09166542
申请日：1998-10-05
申请人： Didier Lattard , Jean-René Lequepeys , Didier Varreau , Norbert Daniele
发明人： Didier Lattard , Jean-René Lequepeys , Didier Varreau , Norbert Daniele
IPC分类号： H04B1500
CPC分类号： H04B1/7107 , H04J13/0022 , H04J13/10
摘要： In order to obtain the signals necessary for the formation of an interference signal corresponding to the multiple access noise, use is made both of the non-coherent part of the receiver, namely the differential demodulation device, and the coherent part thereof, namely the two matched filters performing the correlations. This gives a reliable, precise, clock symbol signal (Hs) and also the reconstituted data (D(I), D(Q)) and the amplitudes of the signals in the two channels (A(I), A(Q)). Formation then takes place of the correction signal by respreading the data (D(I), D(Q)) and the weighting the respread data by the amplitudes (A(I), A(Q)).
摘要翻译：为了获得形成与多址噪声相对应的干扰信号所需的信号，使用接收机的非相干部分即差分解调装置及其相干部分，即两者执行相关性的匹配滤波器。这给出了可靠，精确的时钟符号信号（Hs）以及重建的数据（D（I），D（Q））和两个信道（A（I），A（Q））中的信号的幅度，。然后，通过重叠数据（D（I），D（Q））和通过幅度（A（I），A（Q））对重播数据进行加权来形成校正信号。

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